Standardized flash controller

• US 5,799,168 A
• Filed: 01/05/1996
• Issued: 08/25/1998
• Est. Priority Date: 01/05/1996
• Status: Expired due to Term

• Current Assignee: SanDisk IL Ltd. (Western Digital Corporation)
• Original Assignee: M-Systems Flash Disk Pioneers Ltd. (Western Digital Corporation)
• Inventors: Ban, Amir
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Chow, Christopher S.
• Application Number:
  US08/583,351
• Time in Patent Office: 963 Days
• Field of Search: 395/430, 395/481, 395/483, 395/405, 395/484
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory

Abstract

A flash memory controller operates a flash memory array comprising a plurality of different types of flash memory chips. The CPU interacts with the array by issuing generic commands through a single Memory Technology Driver (MTD), while the controller translates the generic commands into commands specific to the chip comprising the portion of the array being addressed. The controller operates each of the flash chips which comprises the flash memory array, and presents to the CPU a memory system comprised of a single addressable entity. According to a further feature of the invention, the controller is embedded into each of the flash chips in an array in order to further reduce overhead costs.

Claims

1. A flash array controller system, comprising a plurality of flash array controllers, each of said controllers serving to control a flash chip of the flash array, each of said controllers including a translation apparatus for translating commands received from the CPU into commands particular to the flash chip, each of said controllers featuring:

a. a count register,

b. a data register,

c. a status register,

d. a command register that recognizes the following commands;

read;

write;

erase; and

identify;

wherein each of said controllers is located on one of said flash chips of the flash array, and wherein said controller features a protocol for communicating with another of said controllers, said controller system being configured such that flash addresses are divided and assigned to the various flash chips, said controller system featuring a method for summing up the total memory contained in the entire flash array and returning that sum to the CPU in response to an identify command.

2. A flash array controller system, comprising a plurality of flash array controllers, each of said controllers serving to control a flash chip of the flash array, each of said controllers including a translation apparatus for translating commands received from the CPU into commands particular to the flash chip, said translation apparatus being a simple discrete logic for translating commands received from the CPU into commands particular to the flash chip, each of said controllers featuring:

a. a count register,

b. a data register,

c. a status register,

d. a command register that recognizes the following commands;

read;

write;

erase; and

identify;

said controller further comprising particular data embedded into the controller that includes information about the flash chip, said information being at least one from the group consisting of the size of the flash chip, the size of the minimal erasable block, and the programming voltage needed;

wherein each of said controllers is located on one of said flash chips of the flash array, and wherein said controller features a protocol for communicating with another of said controllers, said controller being configured such that flash addresses are divided and assigned to the various flash chips, said controller system featuring a method for summing up the total memory contained in the entire flash array and returning that sum to the CPU in response to an identify command.

3. A flash array controller for controlling a flash array of a plurality of flash chips, the flash chips being of any type, the controller interacting with a driver on a CPU, the controller comprising a command register for receiving commands from the driver on the CPU and translating said commands into commands particular to the flash array, such that the type of flash chip is not restricted by the driver of the CPU, said command register recognizing the following commands:

read, write, erase and identify.

4. The flash array controller of claim 3, wherein said command register translates said commands from the driver on the CPU using discrete logic.

5. The flash array controller of claim 3, wherein said command register translates said commands from the driver on the CPU using a Field Programmable Gate Array (FPGA).

6. The flash array controller of claim 3, wherein said command register translates said commands from the driver on the CPU using an ASIC (Application Specific Integrated Circuit).

7. The flash array controller of claim 3, further comprising a data register for transferring data between the flash array and the controller, and between the CPU and the controller, such that data is transferred for any type of flash chip.

8. The flash array controller of claim 3, further comprising embedded information for transmitting to the CPU in response to said identify command, said embedded information being selected from the group consisting of the size of each individual flash chip, the size of the minimal erasable block, the number of flash chips in the array, the interleaving factor for the flash chips and the required programming voltage for programming the flash chips.

9. The flash array controller of claim 8, wherein said embedded information is hard coded into the controller.

10. The flash array controller of claim 8, wherein said embedded information is set by mechanical jumpers configured to indicate flash array information.

11. The flash array controller of claim 3, wherein the controller, in response to said Identify command from the driver of the CPU, dynamically identifies the number of flash chips and the interleaving factor in the flash array by issuing Read ID commands to ascending flash addresses in order to identify the type of chips present, the size of each individual flash chip, the size of the minimal erasable block and the programming voltage required for programming the flash chips.

12. A flash array controller for controlling a flash array of a plurality of flash chips, the flash chips being of any type, the controller interacting with a driver on a CPU, the controller comprising an address register for assigning an address to each of the plurality of flash chips such that the flash chip is an assigned flash chip, and for receiving a requested address from the driver on the CPU and locating said requested address on said assigned flash chip having said requested address, such that the driver on the CPU is able to issue a command to an address on any of the plurality of flash chips.

13. The flash array controller of claim 12, further comprising a command register for receiving commands from the driver on the CPU and translating said commands into commands particular to the flash array, such that the type of flash chip is not restricted by the driver of the CPU, said command register recognizing the following commands:

read, write, erase and identify.

14. The flash array controller of claim 13, wherein said command register translates said commands from the driver on the CPU using discrete logic.

15. The flash array controller of claim 13, wherein said command register translates said commands from the driver on the CPU using a Field Programmable Gate Array (FPGA).

16. The flash array controller of claim 13, wherein said command register translates said commands from the driver on the CPU using an ASIC (Application Specific Integrated Circuit).

17. The flash array controller of claim 13, further comprising a data register for transferring data between the flash array and the controller, and between the CPU and the controller, such that data is transferred for any type of flash chip.

18. The flash array controller of claim 13, further comprising embedded information for transmitting to the CPU in response to said identify command, said embedded information being selected from the group consisting of the size of each individual flash chip, the size of the minimal erasable block, the number of flash chips in the array, the interleaving factor for the flash chips and the required programming voltage for programming the flash chips.

19. The flash array controller of claim 18, wherein said embedded information is hard coded into the controller.

20. The flash array controller of claim 18, wherein said embedded information is set by mechanical jumpers configured to indicate flash array information.

21. The flash array controller of claim 13, wherein the controller, in response to said Identify command from the driver of the CPU, dynamically identifies the number of flash chips and the interleaving factor in the flash array by issuing Read ID commands to ascending flash addresses in order to identify the type of chips present, the size of each individual flash chip, the size of the minimal erasable block and the programming voltage required for programming the flash chips.

22. A flash array controller for controlling a flash array of a plurality of flash chips, the flash chips being of any type, the controller interacting with a driver on a CPU and with each flash chip in the array, the controller comprising:

(a) a count register for specifying a quantity of bytes for a read/write operation, as said count register recording said quantity of bytes according to a command from the CPU;

(b) a data register for sequentially passing data between the CPU and the flash array;

(c) a status register for giving a status of the flash array to the CPU;

(d) an address register for specifying a flash address for a read/write operation, said flash address being specified by the CPU; and

(e) a command register for receiving commands from the driver on the CPU and translating said commands into commands particular to the flash array, such that the type of flash chip is not restricted by the driver of the CPU, said command register recognizing and translating said commands such that said commands from the driver on the CPU are executed on the flash array, said commands including read, write, erase and identify.

23. The flash array controller of claim 22, wherein said command register translates said commands from the driver on the CPU using discrete logic.

24. The flash array controller of claim 22, wherein said command register translates said commands from the driver on the CPU using a Field Programmable Gate Array (FPGA).

25. The flash array controller of claim 22, wherein said command register translates said commands from the driver on the CPU using an ASIC (Application Specific Integrated Circuit).

26. The flash array controller of claim 22, further comprising embedded information for transmitting to the CPU in response to said identify command, said embedded information being selected from the group consisting of the size of each individual flash chip, the size of the minimal erasable block, the number of flash chips in the array, the interleaving factor for the flash chips and the required programming voltage for programming the flash chips.

27. The flash array controller of claim 26, wherein said embedded information is hard coded into the controller.

28. The flash array controller of claim 26, wherein said embedded information is set by mechanical jumpers configured to indicate flash array information.

29. The flash array controller of claim 22, wherein the controller, in response to said Identify command from the driver of the CPU, dynamically identifies the number of flash chips and the interleaving factor in the flash array by issuing Read ID commands to ascending flash addresses in order to identify the type of chips present, the size of each individual flash chip, the size of the minimal erasable block and the programming voltage required for programming the flash chips.