Multiple thread micro-sequencer apparatus and method with a single processor

• US 5,799,182 A
• Filed: 01/21/1997
• Issued: 08/25/1998
• Est. Priority Date: 01/21/1997
• Status: Expired due to Fees

• Current Assignee: Visteon Global Technologies Incorporated (Visteon Corporation)
• Original Assignee: Ford Motor Company
• Inventors: Jaeckel, Silvia E., Gravenstein, Martin G., Vigil, Michael A.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): VU, VIET DUY
• Application Number:
  US08/786,585
• Time in Patent Office: 581 Days
• Field of Search: 395/561, 395/571, 395/573, 395/595, 395/598, 395/596, 395/379, 395/672, 395/677, 395/678
• US Class Current: 712/245
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

A micro-sequencer apparatus (10) allows a plurality of threads to independently process one or several algorithms using common components by allowing each thread to execute one instruction during a cycle. A thread counter (12) identifies the current thread to allow processing of its instruction. A thread program counter (16) stores the program count or address for the current instruction for the current thread. An instruction memory (20) stores all instructions, and the program count identifies the particular instruction for processing. A processor (26) receives input information unique to the current thread and processes same with the current instruction to produce an output.

Claims

1. A micro-sequencer apparatus for processing multi-threads including multiple data and multiple instructions in parallel on a single processor, said apparatus comprising:

a thread counter (12) for identifying a current thread from a plurality of threads for producing a thread signal representative of said current thread, each thread representing an independent process, for determining subsequent sequence of each of said plurality of threads for subsequent identification as the current thread, and for identifying an input signal associated with said current thread;

a thread program counter (16) for storing a program count for each of said plurality of threads indicating the address location of an executable instruction within the respective independent process, said program count for each current thread being different than said program count for a subsequent thread, and for receiving said thread signal to produce said program count for said current thread;

an instruction memory (20) storing at least one algorithm providing a process and having a plurality of executable instructions for receiving said program count to designate one of said plurality of instructions as a current instruction; and

a processor (20) for receiving said current instruction of said current thread and performing a function of said current instruction with said input to produce an output, said processor being shared to process each of said plurality of threads.

2. A micro-sequencer apparatus as set forth in claim 1 including an instruction register (22) for storing said current instruction from said instruction memory (20).

3. A micro-sequencer apparatus as set forth in claim 2 including an instruction decoder (24) for receiving said current instruction from said instruction register (22) and decoding said current instruction with an input signal for said processor (26).

4. A micro-sequencer apparatus as set forth in claim 3 including a program register (18) for storing said program count for said instruction memory (20).

5. A micro-sequencer apparatus as set forth in claim 4 including a branch logic circuit (28) for receiving said output, said input signal and said current program count and for producing a next program count for storing in said thread program counter (16) associated with said current thread.

6. A micro-sequencer apparatus as set forth in claim 5 including an input multiplexer (14) connected to said plurality of input signals to receive said current thread and to supply one of said input signals associated with said current thread as part of said input.

7. A micro-sequencer apparatus as set forth in claim 6 including an output multiplexer (36) connecting said output signal to a plurality of output lines.

8. A micro-sequencer apparatus as set forth in claim 1 wherein said processor (26) includes a plurality of thread registers (30) associated with different of said plurality of threads to receive said thread signal and to activate only those thread registers (30) associated with said current thread to provide said input.

9. A micro-sequencer apparatus as set forth in claim 8 wherein said processor (26) further includes a plurality of shared registers (32) for storing data during processing.

10. A micro-sequencer apparatus as set forth in claim 9 wherein said processor (26) further includes an arithmetic unit (34) for processing said instructions and performing calculations on said input.

11. A method of sequencing multiple threads including multiple data and multiple instructions in parallel through a single processor, the method including the steps of:

identifying a current thread from a plurality of threads and producing a thread signal, each thread representing an independent process,

determining the subsequent sequence of the remainder of the plurality of threads as for identification as the current thread,

identifying an input signal associated with the current thread,

storing a program count for each of the plurality of threads indicating the address location of an executable instruction within the respective process,

receiving the thread signal to produce a program count for the current thread,

storing at least one algorithm providing the process and having a plurality of executable instructions and receiving the program count to designate one of the instructions as a current instruction, and

receiving and processing the current instruction of the current thread with the input signal to produce an output signal thereon on a single processor, each thread sharing the processor.

12. A method as set forth in claim 11 including the step of storing the program count for the current thread in a separate register.

13. A method as set forth in claim 12 including the step of storing the current instruction in a register.

14. A method as set forth in claim 13 including the step of decoding the current instruction with the input signal for processing.

15. A method as set forth in claim 14 including the step receiving the output signal, input signal, and current program count and producing the next program count for storing for the current thread.

16. A method as set forth in claim 15 including the step of receiving a plurality of input signals and supplying at least one of the input signals based on the selected current thread.

17. A method as set forth in claim 16 including the step of identifying unique registers from a plurality of registers and activating the registers associated with the current thread.

18. A method as set forth in claim 17 including the step of storing the output in the unique registers associated with the current thread.

19. A micro-sequencer apparatus for processing multi-threads including multiple data and multiple instructions, said apparatus comprising:

a thread counter (12) for identifying a current thread from a plurality of threads for producing a thread signal representative of said current thread, for determining subsequent sequence of each of said plurality of threads for subsequent identification as the current thread, and for identifying an input signal associated with said current thread;

a thread program counter (16) for storing a program count for each of said plurality of threads indicating the address of an executable instruction, said program count for each current thread being different than said program count for a subsequent thread, and for receiving said thread signal to produce said program count for said current thread;

an instruction memory (20) storing at least one algorithm having a plurality of executable instructions for receiving said program count to designate one of said plurality of instructions as a current instruction;

a processor (20) for receiving said current instruction and performing a function of said current instruction with said input to produce an output;

an input multiplexer (14) connected to a plurality of input signals to receive said current thread and to supply one of said input signals associated with said current thread as part of said input, the other of said input signals associated with the other threads.

20. A micro-sequencer apparatus as set forth in claim 19 wherein said processor (26) includes a plurality of thread registers (30) associated with different of said plurality of threads to receive said thread signal and to activate only those thread registers (30) associated with said current thread to provide said input.