Method of processing data batch transfer among the memories in a computer system having a hierarchical memory structure

• US 5,799,183 A
• Filed: 05/13/1994
• Issued: 08/25/1998
• Est. Priority Date: 07/27/1993
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Iwashita, Hidetoshi
• Primary Examiner(s): Amsbury, Wayne
• Assistant Examiner(s): LEWIS, CHERYL RENEA
• Application Number:
  US08/242,451
• Time in Patent Office: 1,565 Days
• Field of Search: 395/600, 395/425, 395/650, 395/575, 395/602, 395/604, 395/607, 395/614, 395/706, 395/671
• US Class Current: 1/1
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 8/443 Optimisation

Abstract

A method for optimizing a program by performing a data batch transfer between a first and second memories when data is read from the second memory into the first memory and when the data is written from the first memory into the second memory. The optimization processing includes analyzing the preference order relation of the accesses, in a loop procedure having accesses to array data in the second memory, classifying the array accesses in the loop into groups that need to be shared in the storage regions in which the data are temporarily stored in the first memory, finding the sum of sets of access elements for the accesses pertaining to each of the groups, determining a range of transferring the data, and generating, outside the loop, an instruction code for batchwisely making accesses to the array data on a transfer range pertaining to each of the groups.

Claims

1. A method for optimizing a program having a loop with access elements which access array data in a computer utilizing a high speed local first memory and a global second memory by defining a data batch transfer for use when data is written from the first memory into the second memory and also when the data is read from the second memory into the first memory wherein said second memory and said first memory form a hierarchical memory structure, said method comprising:

analyzing a preference order relation of the array data accesses in the loop;

classifying the array data accesses into groups that can share storage regions in said first memory;

calculating a sum of sets of access elements pertaining to each of the groups and determining a transfer range of array data for transferring into the first memory; and

generating, outside the loop, an instruction code for batchwisely making accesses to the array data in the transfer range for each of the groups.

2. A method according to claim 1, wherein the transfer range includes a read transfer range and a write transfer range, and wherein said step of calculating a sum of sets includes a substep of extracting from the read transfer range, a set of unused access elements from a plurality of sets of access elements referred to in the loop for the array data accesses pertaining to each of said groups, and a substep which finds a sum of sets of access elements for the read transfer range and for the write transfer range for each of the groups, and determines transfer range.

3. A method according to claim 2, wherein said step of generating an instruction code includes a substep which forms, before a corresponding loop, an instruction code that batchwisely accesses the array data in the second memory in said read transfer range, and forms, after said loop, an instruction code that batchwisely accesses the array data in the second memory in said write transfer range.

4. A computer system having a hierarchical memory structure comprising:

at least one processor;

a high speed first memory which is part of a hierarchical memory structure and which said processors accesses;

a second memory which is part of the hierarchical memory structure and works in cooperation with said first memory; and

means for effecting an optimization processing of a program that operates in said computer system;

said means for effecting the optimization processing including;

means for calculating a preference order relation of data array accesses contained in a loop in the program, the loop having access elements which access the data array;

means for classifying the data array accesses in the loop into groups that share storage regions in said first memory;

means for finding a sum of sets of access elements for the data array accesses, pertaining to each of the groups, and determining a transfer range for the array data; and

means for generating an instruction code outside the loop for batchwisely accesses the array data in said memory within a transfer range pertaining to each of said groups.

5. A computer system according to claim 4, wherein said second memory has one of a large capacity and a function of holding the data shared by other processors.

6. A computer system having a hierarchical memory structure comprising:

at least one processor;

a high speed first memory which is part of a hierarchical memory structure which said processor accesses;

a second memory which is part of the hierarchical memory structure and works in cooperation with said first memory; and

means for effecting an optimization processing of a program that operates in said computer system;

said means for effecting the optimization processing including;

means for calculating a preference order relation of data array accesses contained in a loop in the program;

means for classifying the data array accesses in the loop into groups that share storage regions in said first memory;

means for defining a read transfer range including a set of access elements referred to in the loop pertaining to each of the groups and which excludes a set of access elements define prior to the reference, defining a write transfer range, finding the sum of sets of access elements in the read transfer range and the write transfer range for each of the groups, and determining a total range of transferring the data; and

means for generating, before a corresponding loop instruction;

an instruction code that batchwisely accesses the array data in said read transfer range, and forming, after said loop instruction, an instruction code that batchwisely accesses the array data in said write transfer range.

7. A computer system according to claim 6, wherein said second memory has one of a large capacity and a function of holding data shared by other processors.