Non-blocking peripheral access architecture having a register configure to indicate a path selection for data transfer between a master, memory, and an I/O device

• US 5,799,207 A
• Filed: 03/28/1995
• Issued: 08/25/1998
• Est. Priority Date: 03/28/1995
• Status: Expired due to Term

• Current Assignee: Transpacific IP Group Limited
• Original Assignee: Industrial Technology Research Institute
• Inventors: Hsu, Zen-Dar, Chang, Wei-Wen, Wang, Shih-Chieh
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Huang, Po C.
• Application Number:
  US08/413,807
• Time in Patent Office: 1,246 Days
• Field of Search: 370/85.1, 370/364, 395/281, 395/304, 395/308, 395/821, 395/842, 395/200.03, 395/200.07, 395/310, 395/800.15, 395/826, 395/287, 395/309, 395/858, 395/849
• US Class Current: 710/38
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A computer system is disclosed which has a master, such as a processor, a memory, and I/O device, a first transfer path, which includes a bus, and a second transfer path, which includes a transfer interconnection. Transfers between the memory and the I/O device are effected via the first path while transfers between the processor and the I/O device are transferred via the second path. The disparate treatment between these two types of transfers reduces the likelihood that the transfer via the second path is delayed and thereby reduces the likelihood that the master is totally blocked from operation.

Claims

1. In a computer system comprising a master, a memory, an I/O expansion bus, an I/O transfer interconnection not connected to the expansion bus, an I/O device connected to the I/O expansion bus and the I/O transfer interconnection, and a register configured to indicate one of said I/O expansion bus and said I/O transfer interconnection for transfers between said master and said I/O device, a transfer process comprising the steps of:

(a) selecting the I/O device to the I/O expansion bus for performing a transfer on a first path between said I/O device and said memory; and

(b) selecting the I/O device to the one of said I/O expansion bus and said I/O transfer interconnection in accordance with said register for performing a transfer between said master and said I/O device.

3. The process of claim 1, wherein transfers via said second path are initiated by only said master.

4. The process of claim 1, further comprising the step of writing, from said master to a storage location of said register, which storage location corresponds to said I/O device, an indication that said transfer interconnection supports transfers between said master and said I/O device.

5. The process of claim 1, further comprising, for each I/O device, the steps of:

(a) polling said I/O device, via said first path, and

(b) in response to said I/O device failing to respond in said step of polling via said first path, polling said I/O device via said second path.

6. The process of claim 5, further comprising the step of, in response to said I/O device responding to said step of polling via said second path, writing in a storage location of said register, which storage location corresponds to said I/O device, an indication that said second path supports transfers between said master and said I/O device.

7. The process of claim 1, wherein said step of transferring via said second path further comprises the step of transmitting an MIO_-- SEL signal indicating a particular one of two types of registers in said I/O device to be accessed transfer via said second path.

8. The process of claim 1, further comprising the step of after said step of transferring via said second path, transmitting an MIO_-- SEL signal indicating that said transfer via said second path was successful.

9. The process of claim 5, further comprising, for each I/O device, the step of:

in response to said polling via said second path, transmitting said MIO_-- SEL signal.

10. The process of claim 1, wherein a likelihood of processing delay in said master, by transfers via said I/O expansion bus is decreased.

2. A process for transferring data via one of first and second data paths, said first data path including an I/O expansion bus, and said second data path bypassing said I/O expansion bus via a transfer interconnection, said process comprising the steps of:

(a) storing in a register an indication whether said transfer interconnection supports transfers between said master and said I/O device;

(b) if said transfer is between a memory and said I/O device, then performing said transfer via said first path; and

(c) if said transfer is between a master and said I/O device, performing said transfer via said one of first and second data paths in accordance with said indication in said register.

16. The process of claim 2, wherein transfers via said second path are initiated by only said master.

17. The process of claim 2, wherein the step of storing said indication further comprises the step of writing said indication from said master to a storage location of said register, which storage location corresponds to said I/O device.

18. The process of claim 2, wherein said step of storing said indication further comprises, for each I/O device, the steps of:

(a) polling said I/O device, via said first path, and

(b) in response to said I/O device failing to respond in said step of polling via said first path, polling said I/O device via said second path.

19. The process of claim 18, wherein the step of storing said indication further comprises the step of, in response to said I/O device responding to said step of polling via said second path, writing said indication to a storage location of said register, which storage location corresponds to said I/O device.

20. The process of claim 2, wherein said step of transferring via said second path further comprises the step of transmitting an MIO_-- SEL signal indicating a particular one of two types of registers in said I/O device to be accessed transfer via said second path.

21. The process of claim 2, further comprising the step of after transferring data via said second path, transmitting an MIO_-- SEL signal indicating that said transfer via said second path was successful.

22. The process of claim 18, further comprising, for each I/O device, the step of:

in response to said polling via said second path, transmitting said MIO_-- SEL signal.

23. The process of claim 2, wherein a likelihood of processing delay in said master, by transfers via said I/O expansion bus is decreased.

11. A computer system, comprising:

(a) a master,

(b) a memory,

(c) an I/O device,

(d) a register configured to store an indication whether said transfer interconnection supports transfers between said master and said I/O device,

(e) a first data path, including a first bus connected to said I/O device, for performing transfers between said memory and said I/O device and for performing transfers between said master and said I/O device if said indication is that said transfer interconnection fails to support transfers between said master and said I/O device, and

(f) a second data path, including a transfer interconnection connected to said I/O device, for performing transfers between said master and said I/O device if said indication is that said transfer interconnection supports transfers between said master and said I/O device, said second data path not including the first bus.

12. The computer system of claim 11, wherein said transfer interconnection is a second bus.

13. The computer system of claim 12, wherein said second bus comprises:

(a) a plurality of lines for transferring address and data bits of commands and responses, and

(b) a register select line for transferring an indication specifying that said transfer via said plurality of lines accesses either a configuration register or an I/O space register of said I/O device.

14. The computer system of claim 11, further comprising:

(a) a system bus interconnecting said master and said shared memory, and

(b) an I/O bridge connected to said system bus and to both said first bus and said transfer interconnection,

(c) wherein said first path further comprises said system bus and said I/O bridge and wherein said second path further comprises said system bus and said I/O bridge.

15. The computer system of claim 11, wherein said transfer interconnection is a ring connection.

24. The computer system of claim 11, wherein the computer comprises a plurality of I/O devices, at least one I/O device being a non-blocking I/O device and at least one I/O device being a conventional I/O device and wherein each non-blocking I/O device is connected to the first and second data paths and each conventional I/O device is connected only to the first data path.