Inverted field-effect device with polycrystalline silicon/germanium channel

• US 5,801,396 A
• Filed: 06/07/1995
• Issued: 09/01/1998
• Est. Priority Date: 01/18/1989
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Guritz, Elmer H., Blanchard, Richard A., Chan, Tsiu Chiu, Han, Yu-Pin
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US08/488,398
• Time in Patent Office: 1,182 Days
• Field of Search: 257/65, 257/350, 257/368, 257/369, 257/616, 257/903
• US Class Current: 257/65
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

A CMOS device architecture which includes substrate-gated inverted PMOS transistors, as well as bulk NMOS. The inverted-PMOS channels are formed in a different layer from the NMOS gates, and these layers may even have different compositions. Moreover, the NMOS and inverted-PMOS devices have different gate oxide layers, so the thicknesses can be independently optimized. The drain underlap of the inverted device is defined by a patterning step, so it can be increased for high-voltage operation if desired.

Claims

1. An integrated circuit, comprising:

a first field-effect transistor, having

source and drain diffusions of a first conductivity type located in and defining a channel region therebetween in a monocrystalline semiconductor body, and a gate electrode, formed in a first thin-film layer of polycrystalline semiconducting material, which is capacitively coupled to said channel region through a first gate dielectric layer;

a second field-effect transistor, having source and drain diffusions of a second conductivity type located in and defining a channel region therebetween in a second thin-film layer of polycrystalline semiconducting material, and a gate electrode, formed in said monocrystalline body, which is capacitively coupled to said channel region through a second gate dielectric layer;

wherein said first and second gate dielectric layers have different thicknesses at all locations.

2. The integrated circuit of claim 1, wherein said first and second gate dielectrics have different effective thicknesses.

5. The integrated circuit of claim 1, wherein said first polycrystalline film consists essentially of polysilicon.

8. The integrated circuit of claim 1, wherein said first field-effect transistor and said second field-effect transistor provide a latch.

3. An integrated circuit, comprising:

a first field-effect transistor, having

source and drain diffusions of a first conductivity type located in and defining a channel region therebetween in a monocrystalline semiconductor body, and a gate electrode, formed in a first thin-film layer of polycrystalline semiconducting material, which is capacitively coupled to said channel region through a first gate dielectric layer;

a second field-effect transistor, having source and drain diffusions of a second conductivity type located in and defining a channel region therebetween in a second thin-film layer of polycrystalline semiconducting material, and a gate electrode, formed in said monocrystalline body, which is capacitively coupled to said channel region through a second gate dielectric layer;

wherein said first and second gate dielectric layers have different thicknesses; and

wherein said second polycrystalline film, but not said first polycrystalline film, has a total thickness which is less than 1000 Å

.

4. An integrated circuit, comprising:

a first field-effect transistor, having

source and drain diffusions of a first conductivity type located in and defining a channel region therebetween in a monocrystalline semiconductor body, and a gate electrode, formed in a first thin-film layer of polycrystalline semiconducting material, which is capacitively coupled to said channel region through a first gate dielectric layer;

a second field-effect transistor, having source and drain diffusions of a second conductivity type located in and defining a channel region therebetween in a second thin-film layer of polycrystalline semiconducting material, and a gate electrode, formed in said monocrystalline body, which is capacitively coupled to said channel region through a second gate dielectric layer;

wherein said first and second gate dielectric layers have different thicknesses; and

wherein said second polycrystalline film has a total thickness which is less than two-thirds that of said first polycrystalline film.

6. An integrated circuit, comprising:

a first field-effect transistor, having

source and drain diffusions of a first conductivity type located in and defining a channel region therebetween in a monocrystalline semiconductor body, and a gate electrode, formed in a first thin-film layer of polycrystalline semiconducting material, which is capacitively coupled to said channel region through a first gate dielectric layer;

a second field-effect transistor, having source and drain diffusions of a second conductivity type located in and defining a channel region therebetween in a second thin-film layer of polycrystalline semiconducting material, and a gate electrode, formed in said monocrystalline body, which is capacitively coupled to said channel region through a second gate dielectric layer;

where in said first and second gate dielectric layers have different thicknesses; and

wherein said first and second polycrystalline films have different thicknesses.

7. An integrated circuit, comprising:

a first field-effect transistor, having

source and drain diffusions of a first conductivity type located in and defining a channel region therebetween in a monocrystalline semiconductor body, and a gate electrode, formed in a first thin-film layer of polycrystalline semiconducting material, which is capacitively coupled to said channel region through a first gate dielectric layer;

a second field-effect transistor, having source and drain diffusions of a second conductivity type located in and defining a channel region therebetween in a second thin-film layer of polycrystalline semiconducting material, and a gate electrode, formed in said monocrystalline body, which is capacitively coupled to said channel region through a second gate dielectric layer;

wherein said first and second gate dielectric layers have different thicknesses; and

wherein said first and second field-effect transistors are interconnected to provide a CMOS logic gate.

9. An integrated circuit, comprising:

a first field-effect transistor, having source and drain diffusions of a first conductivity type located in and defining a channel region therebetween in a monocrystalline semiconductor body, and a gate electrode, formed in a first thin-film layer of polycrystalline semiconducting material, which is capacitively coupled to said channel region through a first gate dielectric layer;

a second field-effect transistor, having source and drain diffusions of a second conductivity type located in and defining a channel region therebetween in a second thin-film layer of polycrystalline semiconducting material, and a gate electrode, formed in said monocrystalline body, which is capacitively coupled to said channel region through a second gate dielectric layer, wherein said first and second gate dielectrics have different effective thicknesses;

wherein said drain region of said second transistor does not overlie said gate thereof, and said source and drain are asymmetrically located with respect to said gate.

10. An integrated circuit, comprising:

a first field-effect transistor, having source and drain diffusions of a first conductivity type located in and defining a channel region therebetween in a monocrystalline semiconductor body, and a gate electrode, formed in a first thin-film layer of polycrystalline semiconducting material, which is capacitively coupled to said channel region through a first gate dielectric layer;

a second field-effect transistor, having source and drain diffusions of a second conductivity type located in and defining a channel region therebetween in a second thin-film layer of polycrystalline semiconducting material, and a gate electrode, formed in said monocrystalline body, which is capacitively coupled to said channel region through a second gate dielectric layer, wherein said second polycrystalline film, but not said first polycrystalline film, has a total thickness which is less than 1000 Å

;

wherein said drain region of said second transistor does not overlie said gate thereof, and said source and drain are asymmetrically located with respect to said gate.

11. An integrated circuit, comprising:

a first field-effect transistor, having source and drain diffusions of a first conductivity type located in and defining a channel region therebetween in a monocrystalline semiconductor body, and a gate electrode, formed in a first thin-film layer of polycrystalline semiconducting material, which is capacitively coupled to said channel region through a first gate dielectric layer;

a second field-effect transistor, having source and drain diffusions of a second conductivity type located in and defining a channel region therebetween in a second thin-film layer of polycrystalline semiconducting material, and a gate electrode, formed in said monocrystalline body, which is capacitively coupled to said channel region through a second gate dielectric layer, wherein said second polycrystalline film has a total thickness which is less than two-thirds that of said first polycrystalline film;

wherein said drain region of said second transistor does not overlie said gate thereof, and said source and drain are asymmetrically located with respect to said gate.

12. An integrated circuit, comprising:

a first field-effect transistor, having source and drain diffusions of a first conductivity type located in and defining a channel region therebetween in a monocrystalline semiconductor body; and

a gate electrode, formed in a first thin-film layer of polycrystalline semiconducting material, which is capacitively coupled to said channel region through a first gate dielectric layer;

a second field-effect transistor, having source and drain diffusions of a second conductivity type located in and defining a channel region therebetween in a second thin-film layer of polycrystalline semiconducting material, and a gate electrode, formed in said monocrystalline body, which is capacitively coupled to said channel region through a second gate dielectric layer, wherein said first and second polycrystalline films have different thicknesses;

wherein said drain region of said second transistor does not overlie said gate thereof, and said source and drain are asymmetrically located with respect to said gate.

13. An integrated circuit, comprising:

a first field-effect transistor, having source and drain diffusions of a first conductivity type located in and defining a channel region therebetween in a monocrystalline semiconductor body near a first surface thereof, and a gate electrode, formed in a first thin-film layer of polycrystalline semiconducting material, which is capacitively coupled to said channel region through a first gate dielectric layer;

a second field-effect transistor, having source and drain diffusions of a second conductivity type located in and defining a channel region therebetween in a second thin-film layer of polycrystalline semiconducting material, and a gate electrode, formed in said monocrystalline body, which is capacitively coupled to said channel region through a second gate dielectric layer; and

a third field-effect transistor, having source diffusions of said first conductivity type located near said first surface of said monocrystalline body, and a gate positioned to control current flow from said source into said monocrystalline body away from said first surface thereof; and

a fourth transistor, having source and drain diffusions of said second conductivity type located in said monocrystalline body;

said second and third transistors being connected to define a high-voltage driver stage, and said first and fourth transistors being connected to define a low-voltage inverter which is operatively connected to drive said gate terminals of said second and third transistors.

14. The integrated circuit of claim 13, wherein said third transistor is a DMOS transistor.

15. The integrated circuit of claim 13, wherein said first and second gate dielectrics have different effective thicknesses.

16. The integrated circuit of claim 13, wherein said second polycrystalline film, but not said first polycrystalline film, comprises at least 10% germanium.

17. The integrated circuit of claim 13, wherein said second polycrystalline film, but not said first polycrystalline film, has a total thickness which is less than 1000 Å

.

18. The integrated circuit of claim 13, wherein said second polycrystalline film has a total thickness which is less than two-thirds that of said first polycrystalline film.

19. The integrated circuit of claim 13, wherein said first polycrystalline film consists essentially of polysilicon.

20. The integrated circuit of claim 13, wherein said first and second polycrystalline films have different thicknesses.

21. The integrated circuit of claim 14, wherein said first field-effect transistor and said second field-effect transistor to provide a latch.

22. The integrated circuit of claim 13, wherein said second polycrystalline film comprises at least about 10% at of a semiconductor other than silicon, and said second gate dielectric is more than 99% at silicon dioxide.