Insulated gate semiconductor device and method of manufacturing the same

• US 5,801,408 A
• Filed: 02/13/1996
• Issued: 09/01/1998
• Est. Priority Date: 07/21/1995
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): Abraham, Fetsum
• Application Number:
  US08/601,161
• Time in Patent Office: 931 Days
• Field of Search: 257/132, 257/133, 257/212, 257/220, 257/242, 257/262, 257/263, 257/302, 257/328, 257/330, 257/332, 257/368, 257/244
• US Class Current: 257/212
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A parasitic transistor of an insulated gate semiconductor device does not easily turn on, so that an SOA of the insulated gate semiconductor device is improved. P⁺ semiconductor layers (45) having a higher impurity concentration than that N⁺ emitter layers (44) are disposed so that the P⁺ semiconductor layers (45) overlap adjacent edges of the N⁺ emitter layers (44) of a U-type IGBT and so that bottom portions of the P⁺ semiconductor layers (45) contact P base layers (43). An emitter electrode (51) contacts the P base layers (43) through the P⁺ semiconductor layers (45). A trench pitch is small, and therefore, a parasitic transistor which is formed by an N⁺ emitter region (4), a P base layer (3) and an N^- layer (2) does not easily turn on.

Claims

1. An insulated gate semiconductor device, comprising:

a first semiconductor layer of a first conductivity type, said first semiconductor layer including a first major surface and a second major surface;

a second semiconductor layer of a second conductivity type which is disposed on said first major surface of said first semiconductor layer, said second semiconductor layer having a low impurity concentration;

a third semiconductor layer of the first conductivity type which is disposed on a surface of said second semiconductor layer;

a fourth semiconductor layer of the second conductivity type which is selectively disposed on a portion of a surface of said third semiconductor layer;

a groove-shaped inner wall being at least one in number defining an opening which opens in a surface of said fourth semiconductor layer so as to extend in a direction along said surface of said fourth semiconductor layer, said groove-shaped inner wall extending along a depth direction thereof from said surface of said fourth semiconductor layer to said second semiconductor layer;

a fifth semiconductor layer of the first conductivity type which is disposed on said surfaces of said third and said fourth semiconductor layers to extend across said third and said fourth semiconductor layers, a junction between said fifth semiconductor layer and said fourth semiconductor layer being exposed to a surface, a bottom surface of said fifth semiconductor layer being located at a shallower position than a bottom surface of said fourth semiconductor layer, said fifth semiconductor layer having a higher impurity concentration than said fourth semiconductor layer;

an insulation film covering said inner wall and a surface of said fourth semiconductor layer which is continuous to said inner wall and is in the vicinity of said opening;

a control electrode which is disposed on a surface of said inner wall through said insulation film;

a first major electrode which is disposed on said surfaces of said fourth and said fifth semiconductor layers; and

a second major electrode which is disposed on said second major surface of said first semiconductor layer.

2. The insulated gate semiconductor device of claim 1, wherein said groove-shaped inner wall is groove-shaped inner walls plural in number, and an exposed surface of said fifth semiconductor layer between adjacent two of said groove-shaped inner walls extends along said groove-shaped inner walls.

3. The insulated gate semiconductor device of claim 2, wherein said exposed surface of said fifth semiconductor layer has a scattered configuration.

4. The insulated gate semiconductor device of claim 1, wherein the impurity concentration of said fifth semiconductor layer is about twice higher than the impurity concentration of said fourth semiconductor layer.

5. The insulated gate semiconductor device of claim 1, wherein at least a portion of said control electrode has a recessed surface which is recessed from a surface of a portion of said insulation film covering said surface of said fourth semiconductor layer.

6. The insulated gate semiconductor device of claim 5, wherein said portion of said control electrode is adjacent to a portion of said insulation film covering said inner wall.

7. An insulated gate semiconductor device, comprising:

a first semiconductor layer of a first conductivity type, said first semiconductor layer including a first major surface and a second major surface;

a second semiconductor layer of a second conductivity type which is disposed on said first major surface of said first semiconductor layer, said second semiconductor layer having a low impurity concentration;

a third semiconductor layer of the first conductivity type which is disposed on a surface of said second semiconductor layer;

a fourth semiconductor layer of the second conductivity type which is selectively disposed on a portion of a surface of said third semiconductor layer;

groove-shaped inner walls plural in number, each one thereof defining an opening which opens in a surface of said fourth semiconductor layer so as to extend in a direction along said surface of said fourth semiconductor layer, said groove-shaped inner walls extending along a depth direction thereof from said surface of said fourth semiconductor layer to said second semiconductor layer;

a fifth semiconductor layer of the first conductivity type which is disposed on said surfaces of said third and said fourth semiconductor layers which are present between adjacent two of said groove-shaped inner walls so as to extend across said third and said fourth semiconductor layers in a configuration scattered along said adjacent two, a junction between said fifth semiconductor layer and said fourth semiconductor layer being exposed to a surface, said fifth semiconductor layer having a higher impurity concentration than said fourth semiconductor layer;

an insulation film covering said groove-shaped inner walls, a portion of a surface of said fourth semiconductor layer which is continuous to and adjacent to said groove-shaped inner walls, and a portion of a surface of said fifth semiconductor layer which is adjacent to said portion of said surface of said fourth semiconductor layer;

a control electrode which is disposed on surfaces of said groove-shaped inner walls through said insulation film;

a first major electrode which is disposed on said surfaces of said fourth and said fifth semiconductor layers; and

a second major electrode which is disposed on said second major surface of said first semiconductor layer.

8. The insulated gate semiconductor device of claim 7, wherein the impurity concentration of said fifth semiconductor layer is about twice higher than the impurity concentration of said fourth semiconductor layer.

9. The insulated gate semiconductor device of claim 7, wherein at least a portion of said control electrode has a recessed surface which is recessed from a surface of a portion of said insulation film covering said surface of said fourth semiconductor layer.

10. The insulated gate semiconductor device of claim 9, wherein said portion of said control electrode is adjacent to a portion of said insulation film covering said inner wall.

11. An insulated gate semiconductor device, comprising:

a first semiconductor layer of a first conductivity type, said first semiconductor layer including a first major surface and a second major surface;

a second semiconductor layer of a second conductivity type which is disposed on said first major surface of said first semiconductor layer, said second semiconductor layer having a low impurity concentration;

a third semiconductor layer of the first conductivity type which is disposed on a surface of said second semiconductor layer;

fourth semiconductor layers of the second conductivity type which are plural in number and are disposed parallel to each other in the shape of columns on a portion of a surface of said third semiconductor layer;

groove-shaped inner walls plural in number defining openings respectively which open in respective surfaces of said fourth semiconductor layers so as to extend along said columns of said fourth semiconductor layers, said groove-shaped inner walls extending along a depth direction thereof from said surfaces of said fourth semiconductor layers to said second semiconductor layer;

a fifth semiconductor layer of the first conductivity type which is disposed on said surfaces of said third and said fourth semiconductor layers to extend across said third and said fourth semiconductor layers, a junction between said fifth semiconductor layer and said fourth semiconductor layers being exposed to a surface, a bottom surface of said fifth semiconductor layer being located at a shallower position than bottom surfaces of said fourth semiconductor layers, said fifth semiconductor layer having a higher impurity concentration than said fourth semiconductor layers;

an insulation film covering said groove-shaped inner walls and surfaces of said fourth semiconductor layers which are in the vicinity of said openings and are continuous to said groove-shaped inner walls;

a control electrode which is disposed on surfaces of said groove-shaped inner walls through said insulation film;

an interlayer insulation film which is disposed on a surface of said control electrode;

a first major electrode which is disposed on said surfaces of said fourth and said fifth semiconductor layers and said interlayer insulation film; and

a second major electrode which is disposed on said second major surface of said first semiconductor layer.

12. The insulated gate semiconductor device of claim 11, wherein said fifth semiconductor layer is disposed in a scattered configuration along said fourth semiconductor layers.

13. The insulated gate semiconductor device of claim 12, wherein in said surface of said third semiconductor layer, said fourth semiconductor layers further include a plurality of link portions linking those adjacent portions of said fourth semiconductor layers which are disposed in the shape of columns, in a scattered configuration, so that a surface configuration of said fourth semiconductor layers is a ladder-like configuration in areas which are sandwiched by adjacent two of said groove-shaped inner walls.

14. The insulated gate semiconductor device of claim 11, wherein at least a portion of said control electrode has a recessed surface which is recessed from a surface of a portion of said insulation film covering said surface of said fourth semiconductor layer.

15. The insulated gate semiconductor device of claim 14, wherein said portion of said control electrode is adjacent to a portion of said insulation film covering said inner wall.

16. An insulated gate semiconductor device, comprising:

a first semiconductor layer of a first conductivity type, said first semiconductor layer including a first major surface and a second major surface;

a second semiconductor layer of a second conductivity type which is disposed on said first major surface of said first semiconductor layer, said second semiconductor layer having a low impurity concentration;

a third semiconductor layer of the first conductivity type which is disposed on a surface of said second semiconductor layer;

fourth semiconductor layers of the second conductivity type which are plural in number and are disposed parallel to each other in the shape of columns on a portion of a surface of said third semiconductor layer;

groove-shaped inner walls plural in number defining openings respectively which open in respective surfaces of said fourth semiconductor layers so as to extend in a direction along said columns of said fourth semiconductor layers, said groove-shaped inner walls extending along a depth direction thereof from said surfaces of said fourth semiconductor layers to said second semiconductor layer;

a fifth semiconductor layer of the first conductivity type which is disposed in a scattered configuration along said fourth semiconductor layers and on said surfaces of said third and said fourth semiconductor layers to extend across said third and said fourth semiconductor layers, a junction between said fifth semiconductor layer and said fourth semiconductor layers being exposed to a surface, said fifth semiconductor layer having a higher impurity concentration than said fourth semiconductor layers;

an insulation film covering said groove-shaped inner walls, surfaces of said fourth semiconductor layers which are continuous to, adjacent to, and lying along said groove-shaped inner walls, and a portion of a surface of said fifth semiconductor layer which is in the vicinity of said fourth semiconductor layers;

a control electrode which is disposed on surfaces of said groove-shaped inner walls through said insulation film;

an interlayer insulation film which is disposed on a surface of said control electrode;

a first major electrode which is disposed on said surfaces of said fourth and said fifth semiconductor layers and said interlayer insulation film; and

a second major electrode which is disposed on said second major surface of said first semiconductor layer.

17. The insulated gate semiconductor device of claim 16, wherein in said surface of said third semiconductor layer, said fourth semiconductor layers further include a plurality of link portions linking those adjacent portions of said fourth semiconductor layers which are disposed in the shape of columns, in a scattered configuration, so that a surface configuration of said fourth semiconductor layers is a ladder-like configuration in areas which are sandwiched by adjacent two of said groove-shaped inner walls.

18. The insulated gate semiconductor device of claim 16, wherein at least a portion of said control electrode has a recessed surface which is recessed from a surface of a portion of said insulation film covering said surface of said fourth semiconductor layer.

19. The insulated gate semiconductor device of claim 18, wherein said portion of said control electrode is adjacent to a portion of said insulation film covering said inner wall.

20. An insulated gate semiconductor device, comprising:

a first semiconductor layer of a first conductivity type, said first semiconductor layer including a first major surface and a second major surface;

a second semiconductor layer of a second conductivity type which is disposed on said first major surface of said first semiconductor layer, said second semiconductor layer having a low impurity concentration;

a third semiconductor layer of the first conductivity type which is disposed on a surface of said second semiconductor layer;

a fourth semiconductor layer of the second conductivity type which is formed on a surface of said third semiconductor layer so as to leave an exposed surface of said third semiconductor layer in a scattered configuration;

a groove-shaped inner wall being at least one in number defining an opening which opens in a surface of said fourth semiconductor layer so as to extend in a direction along said surface of said fourth semiconductor layer, said groove-shaped inner wall extending along a depth direction thereof from said surface of said fourth semiconductor layer to said second semiconductor layer;

an insulation film covering said groove-shaped inner wall, a portion of a surface of said fourth semiconductor layer which is in the vicinity of said opening and is continuous to said inner wall, and a portion of a surface of said third semiconductor layer which is adjacent to said fourth semiconductor layer;

a control electrode which is disposed on surfaces of said groove-shaped inner walls through said insulation film;

a first major electrode which is disposed on said surfaces of said fourth and said fifth semiconductor layers and said interlayer insulation film; and

a second major electrode which is disposed on said second major surface of said first semiconductor layer.

21. The insulated gate semiconductor device of claim 20, wherein said groove-shaped inner wall is groove-shaped inner walls plural in number, an exposed surface of said third semiconductor layer is disposed between and along adjacent two of said groove-shaped inner walls, and extends in a longitudinal direction of said adjacent two.

22. The insulated gate semiconductor device of claim 21, wherein a surface configuration of said fourth semiconductor layer is a ladder-like configuration in areas which are sandwiched by said adjacent two.

23. The insulated gate semiconductor device of claim 20, wherein at least a portion of said control electrode has a recessed surface which is recessed from a surface of a portion of said insulation film covering said surface of said fourth semiconductor layer.

24. The insulated gate semiconductor device of claim 23, wherein said portion of said control electrode is adjacent to a portion of said insulation film covering said inner wall.