Semiconductor device having a capacitance element with excellent area efficiency

• US 5,801,412 A
• Filed: 07/23/1996
• Issued: 09/01/1998
• Est. Priority Date: 09/04/1995
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tobita, Youichi
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Giordana, Adriana
• Application Number:
  US08/681,442
• Time in Patent Office: 770 Days
• Field of Search: 257/298-300, 257/304-308, 257/263, 257/905, 257/908, 361/321.3, 326/68, 326/149, 365/182
• US Class Current: 257/296
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench
• CPC Class Codes: Y10S 257/908 Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Abstract

N type impurity regions are formed at the surface of N well similarly to a DRAM memory cell. Electrode layers corresponding to storage nodes and conductive layers 9a and 9b corresponding to cell plates are formed for predetermined impurity regions among the impurity regions. Conductive layers are isolated from each other electrically in a DC fashion and connected to electrode nodes VA and VB, respectively. The sets of capacitors formed by a predetermined number of memory cell capacitors connected in parallel through the N well are connected in series. As a result, a capacitor with excellent area efficiency which utilizes the characteristics of the memory cell capacitor can be realized.

Claims

1. A semiconductor device including a capacitance having one and another electrodes, said capacitance comprising:

a first capacitance element and a second capacitance element connected in series between said one and another electrodes;

said first capacitance element including

(a) a first group of a plurality of first impurity regions of a first conductivity type arranged at a surface of a first semiconductor substrate region of the first conductivity type and spaced apart from each other and electrically connected with an electrically conductive path connected to each other through the first semiconductor substrate region,

(b) a first group of a plurality of first conductive layers, each conductive layer electrically connected to a predetermined corresponding first impurity region of said first group, formed having predetermined shapes on the surface of said first semiconductor substrate region an separated from each other, and

(c) a second conductive layer arranged to face the first conductive, layers of said first group with a first insulating layer interposed therebetween, and,

said second capacitance element comprising

(d) a second group of a plurality of first impurity regions the first conductivity type arranged at a surface of a second semiconductor substrate region of the first conductivity type and spaced apart from each other and electrically connected to each other through the second semiconductor substrate region,

(e) a second group of a plurality of first conductive layer, each conductive layer electrically connected to a predetermined corresponding first impurity region of said second group, formed having predetermined shapes on the surface of said second semiconductor substrate region, and separated from each other, and

(f) a third conductive layer arranged to face the first conductive layers of said second group with a second insulating film interposed therebetween.

2. The semiconductor memory device according to claim 1, wherein said second conductive layer is isolated from said third conductive layer, said first semiconductor substrate region and said second semiconductor substrate region constitute a common substrate region, and said second and third conductive layers are electrically connected to said one and another electrodes, respectively.

3. The semiconductor device according to claim 2, further comprising a pad electrically connected to said common semiconductor substrate region.

4. The semiconductor device according to claim 2, further comprising a switching element coupled to receive a test mode instruction signal instructing a predetermined test mode operation to be performed when active, and responsive to activation of the test mode instruction signal for electrically connecting said common semiconductor substrate region to an external terminal.

5. The semiconductor device according to claim 2, further comprising a second impurity region of the first conductivity type formed between said first and second groups at the surface of the common semiconductor substrate region.

6. The semiconductor memory device according to claim 1, wherein said second conductive layer is isolated from said third conductive layer, said first and second semiconductor regions are formed separated from each other, said first semiconductor substrate region is electrically connected to said third conductive layer through an interconnection, and said second conductive layer and said second substrate region are electrically connected to said one and another electrodes.

7. The semiconductor device according to claim 6, further comprising a second impurity region of the first conductive type formed at the surface of said first semiconductor substrate region and electrically connected to said third conductive layer.

8. The semiconductor memory device according to claim 1, wherein said second and third conductive layers are electrically connected to constitute a common conductive layer, said first and second substrate regions are electrically isolated from each other and are electrically connected to said one and another electrodes, respectively.

9. The semiconductor device according to claim 8, further comprising a pad electrically connected to said second and third conductive layers.

10. The semiconductor device according to claim 8, further comprising a switching element coupled to receive a test mode instruction signal instructing a predetermined test mode operation to be performed when active, and responsive to activation of the test mode instruction signal for electrically connecting said second and third conductive layers to an external pin.

11. The semiconductor memory device according to claim 1, wherein said plurality of first conductive layers are connected to said first impurity regions, respectively.

12. The semiconductor memory device according to claim 1, further comprising a fourth conductive layer formed to have a prescribed shape between adjacent first impurity regions among said plurality of first impurity regions in said first and second groups on the surface of said semiconductor substrate region with a fourth insulating film interposed between the fourth conductive layer and said semiconductor substrate region.

13. The semiconductor device according to claim 12, wherein said fourth conductive layers are divided into a first group of fourth conductive layers electrically connected to said second conductive layer and a second group of fourth conductive layers electrically connected to said third conductive layer.

14. The semiconductor device according to claim 13, wherein said first impurity regions are arranged in a matrix of rows and columns and said fourth conductive layer is arranged to extend in a row direction.

15. The semiconductor device according to claims 12, further comprising

a plurality of memory cells arranged in a matrix and formed on a semiconductor substrate region of- a second conductivity type separated from said capacitance, and each having (a) third and fourth impurity regions of the first conductivity type arranged to be isolated from each other on the surface of said semiconductor substrate region of the second conductivity type, (b) a gate electrode layer formed between said third and fourth impurity regions on the substrate region, (c) a sixth conductive layer serving as a storage node electrically connected to said third impurity region, and (d) a seventh conductive layer arranged to face said sixth conductive layer with an insulating film interposed therebetween and serving as a cell plate electrode layer receiving a predetermined voltage, wherein

said first conductive layer is formed of an interconnection layer same as said sixth conductive layer,

said second and third conductive layers are formed of an interconnection layer same as said seventh conductive layer, and

said fourth conductive layer is formed of an interconnection layer same as said gate electrode layer.

16. The semiconductor device according to claim 1, further comprising a fifth conductive layer formed on said first and second semiconductor substrate regions and electrically connected to predetermined first impurity regions among said plurality of first impurity regions for electrically interconnecting said predetermined first impurity regions in each of said first and second groups.

17. The semiconductor device according to claim 16, wherein said first impurity regions are arranged in a matrix of rows and columns and said fifth conductive layer is arranged corresponding to each column and extending in a column direction.

18. The semiconductor device according to claim 17, further comprising an interconnection for electrically interconnecting portions of the fifth conductive layer on the columns in each of said first and second groups.

19. The semiconductor device according to claims 16, further comprising

a plurality of memory cells arranged in a matrix and formed on a semiconductor substrate region of a second conductivity type separated from said capacitance, and each having (a) third and fourth impurity regions of the first conductivity type arranged to be isolated from each other on the surface of said semiconductor substrate region of the second conductivity type, (b) a gate electrode layer formed between said third and fourth impurity regions on the substrate region, (c) a sixth conductive layer serving as a storage node electrically connected to said third impurity region, and (d) a seventh conductive layer arranged to face said sixth conductive layer with an insulating film interposed therebetween and serving as a cell plate electrode layer receiving a predetermined potential, wherein

said first conductive layer is formed of an interconnection layer same as said sixth conductive layer,

said second and third conductive layers are formed of an interconnection layer same as said seventh conductive layer, and

said fifth conductive layer is formed of an interconnection layer same as an eighth conductive layer serving as a bit line electrically connected to the column of memory cells.

20. The semiconductor device according to claim 16, further comprising a pad electrically connected to said fifth conductive layer.

21. The semiconductor device according to claim 16, further comprising a switching element coupled to receive a test mode instruction signal instructing a predetermined test mode operation to be performed when active, and responsive to activation of the test mode instruction signal for electrically connecting said fifth conductive layer to an external terminal.

22. The semiconductor device according to claim 16, further comprising an interconnection for electrically interconnecting said fifth conductive layer in each of said first and second groups to constitute a common conductive layer.

23. The semiconductor device according to claim 16, wherein said fifth conductive layer in said first group is isolated from said fifth conductive layer in said second group.

24. The semiconductor device according to claim 1, further comprising an element isolation insulating film formed at the surface of said first and second semiconductor substrate region between a first impurity region connected to a first conductive layer of said first group and a first impurity region connected to first conductive layers of said second group.

25. The semiconductor device according to claim 1, further comprising

clock application means for applying a clock signal to said one electrode, and

voltage generation means for generating a predetermined potential in accordance with a potential of said another electrode.

26. The semiconductor device according to claim 1, further comprising

a plurality of memory cells arranged in a matrix of rows and columns and formed on a semiconductor substrate region of a second conductivity type separated from said capacitance, and each having (a) third and fourth impurity regions of the first conductivity type arranged to be isolated from each other on the surface of said semiconductor substrate region of the second conductivity type, (b) a gate electrode layer formed between said third and fourth impurity regions on the substrate region, (c) a sixth conductive layer serving as a storage node electrically connected to said third impurity region, and (d) a seventh conductive layer arranged to face said sixth conductive layer with a fourth insulating film interposed therebetween and serving as a cell plate electrode layer for receiving a predetermined potential, wherein

said first conductive layer is formed of an interconnection layer same as said sixth conductive layer, and

said second and third conductive layers are formed of an interconnection layer same as said seventh conductive layer.