Self-aligned power MOSFET device with recessed gate and source

• US 5,801,417 A
• Filed: 08/13/1993
• Issued: 09/01/1998
• Est. Priority Date: 05/17/1988
• Status: Expired due to Term

• Current Assignee: Microsemi Corporation (Microchip Technology Incorporated)
• Original Assignee: Advanced Power Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Meyer, Theodore O., Tsang, Dah Wen, Pike, Douglas A. Jr., Mosier, John W. II
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/106,406
• Time in Patent Office: 1,845 Days
• Field of Search: 257/329, 257/330, 257/331, 257/332, 257/333
• US Class Current: 257/333
• CPC Class Codes: H01L 21/033 comprising inorganic layers
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28'"'"') between spacer inner surfaces (48). This area is doped to form a source layer (72) atop the body layer (26'"'"') and then trenched to form a second trench (80) having sidewalls aligned to the spacer inner surfaces. Second trench (80) defines vertically-oriented source and body layers (86, 90) stacked along gate oxide layer (60) to form vertical channels on opposite sides of second trench (80). Layers (86, 90) have a lateral thickness (88) established by the predetermined spacing of the inner and outer surfaces of the sidewall spacers. Source conductor (94) in the second trench contacts the N-source and P-body layers, and an enhanced P+ region at the base of the second trench.

Claims

1. A recessed gate field effect power MOS device having a vertically oriented channel comprising:

a semiconductor substrate including first and second laterally-extending layers of first and second opposite polarity dopants respectively, the first layer defining a body layer and the second layer defining an underlying drain or base layer;

a first trench having sidewalls extending depthwise from an upper surface of the substrate at least through the body layer to a bottom wall at a first predetermined depth from the upper surface of the semiconductor substrate;

a gate oxide layer on the first trench sidewalls and bottom wall;

a gate conductor filling the first trench depthwise to at least an elevation of the upper surface of the semiconductor substrate and contacting the gate oxide layer on the trench sidewalls;

a second trench having sidewalls extending depthwise from the upper surface of the semiconductor substrate to a bottom wall at a second predetermined depth, the first trench and the second trench being spaced apart by a predetermined lateral distance;

a vertically oriented layer of semiconductor substrate extending upward along the gate oxide layer on each of the opposite sides of the first trench from the body layer to the upper surface of the semiconductor substrate; and

a vertically-extending source conductor contacting the bottom wall and sidewalls of the second trench including the vertically oriented layer on a side opposite the gate oxide layer and gate conductor;

each vertically oriented layer including a first vertical layer portion contiguous with the body layer doped with said first polarity dopant to a first doping concentration to define an active body region including a vertical channel and a second vertical layer portion atop the first vertical layer portion and forming a PN junction therewith;

the second vertical layer portion being doped with said second polarity dopant to form a source region contacting the active body region, and the source conductor electrically shorting the source region to the active body region across the PN junction;

the gate conductor including upper and lower portions vertically stacked within the first trench and respectively contacting first and second portions of the gate oxide layer, and an insulative layer extending laterally between the sidewalls of the first trench to separate the upper and lower portions of the gate conductor so as to electrically isolate said upper and lower portions of the gate conductor from each other within the substrate.

2. A recessed gate field effect power MOS device according to claim 1 in which the gate oxide layer second portion has a first thickness in a lower portion of the first trench and the gate oxide layer first portion has a second thickness in an upper portion of the first trench, the first thickness being greater than the second thickness so that the second portion of the gate oxide layer insulates the second layer from the lower portion of the gate conductor thereby increasing resistance to high voltage rupture of the gate oxide layer while the first portion of the gate oxide layer is thinner than the second portion along the channel region to effect high channel conductance.

3. A recessed gate field effect power MOS device according to claim 2 including an enhanced portion of the body layer extending horizontally and confined to the bottom of the second trench and contained within the body layer, in contact with the source conductor along the bottom wall, being doped to a second doping concentration greater than the first doping concentration and sufficient to reduce pinched base resistance and thereby prevent parasitic bipolar turn-on in the presence of avalanche current.