High voltage power integrated circuit with level shift operation and without metal crossover

• US 5,801,418 A
• Filed: 02/03/1997
• Issued: 09/01/1998
• Est. Priority Date: 02/12/1996
• Status: Expired due to Term

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Ranjan, Niraj
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/794,319
• Time in Patent Office: 575 Days
• Field of Search: 257/336, 257/344, 257/370, 257/373, 257/379, 257/380, 257/408, 257/536
• US Class Current: 257/336
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H01L 27/0738 in combination with resistors only
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Level shift devices are formed in the high voltage termination region of an integrated circuit. The level shift devices provide a connection between the higher voltage, floating circuit and a ground referenced lower voltage circuit. The structure of the level shift devices eliminates the need for a high voltage connector to cross over the low voltage connector.

Claims

1. A level shift device for electrically coupling a floating voltage circuit with a relatively lower voltage circuit each formed on a common substrate of semiconductor material with said level shift circuit, said level shift circuit comprising:

a layer of semiconductor material disposed atop said substrate, said semiconductor material being of a first conductivity type and being lightly doped and having an upper surface;

a base region of a second conductivity type opposite to that of said first conductivity type and extending into the upper surface of said layer of semiconductor material to a given depth;

a source region of said first conductivity type formed in said base region and defining a surface channel region between said source region and said layer of semiconductor material;

a source electrode connected to said source region and electrically coupled to said lower voltage circuit;

a gate insulation layer disposed over said channel region;

a conductive gate layer disposed over said gate insulation layer;

a drain contact diffusion region of said first conductivity type formed in said upper surface of said layer of semiconductor material and being laterally spaced away from said base region;

a drain electrode connected to said drain contact diffusion region;

a further diffusion region of said first conductivity type formed in said upper surface of said layer of semiconductor material and being laterally spaced away from said drain region and further away from said base region, the portion of said layer of semiconductor material located between said drain contact diffusion region and said further diffusion region defining a conduction region;

an insulating layer formed atop said upper surface of said layer of semiconductor material and between said drain region and said further diffusion region;

a contact electrode disposed atop said further diffusion region and electrically coupled to said floating voltage circuit; and

a conducting resistor layer disposed over said insulating layer between said drain electrode and said contact electrode, thereby defining a resistor that is arranged electrically parallel with said conduction region of said layer of semiconductor material;

the resistance of said conduction region being greater than the resistance of said conductive resistor layer.

2. The device of claim 1 further comprising a diffusion region of said second conductivity type formed in said upper surface of said layer of semiconductor material to a predetermined depth and being located beneath said insulating layer such that the conduction region in said layer of semiconductor material is reduced.

3. The device of claim 1 further comprising another body region of said second conductivity type formed in said upper surface of said layer of semiconductor material and disposed between said body region and said drain contact diffusion region.

4. The device of claim 3 further comprising a further metal contact disposed atop at least a portion of said another body region.

5. The device of claim 4 wherein said further metal contact is electrically connected to said source electrode.

6. The device of claim 3 further comprising a resurf region of said second conductivity type formed in said upper surface of said layer of semiconductor material and disposed between said another body region and said drain diffusion region and in contact with said another body region.

7. The device of claim 1 wherein said source contact electrode further contacts a portion of said body region.

8. The device of claim 1 further comprising a heavily doped spacer region of said second conductivity type formed in said layer of semiconductor material and extending into the substrate for electrically isolating said device.

9. An integrated circuit comprising:

a floating voltage circuit;

a relatively lower voltage circuit; and

a level shift device formed in a common substrate with said floating voltage circuit and said lower voltage circuit and comprising;

a layer of semiconductor material disposed atop said substrate, said semiconductor material being of a first conductivity type and being lightly doped and having an upper surface;

a base region of a second conductivity type opposite to that of said first conductivity type and extending into the upper surface of said layer of semiconductor material to a given depth;

a source region of said first conductivity type formed in said base region and defining a surface channel region between said source region and said layer of semiconductor material;

a source electrode connected to said source region and electrically coupled to said lower voltage circuit;

a gate insulation layer disposed over said channel region;

a conductive gate layer disposed over said gate insulation layer;

a drain contact diffusion region of said first conductivity type formed in said upper surface of said layer of semiconductor material and being laterally spaced away from said base region;

a drain electrode connected to said drain contact diffusion region;

a further diffusion region of said first conductivity type formed in said upper surface of said layer of semiconductor material and being laterally spaced away from said drain region and further away from said base region, the portion of said layer of semiconductor material located between said base region and said further diffusion region defining a conduction region;

an insulating layer formed atop said upper surface of said layer of semiconductor material and between said drain region and said further diffusion region;

a contact electrode disposed atop said further diffusion region and electrically coupled to said floating voltage circuit; and

a conducting resistor layer disposed over said insulating layer between said drain electrode and said contact electrode, thereby defining a resistor that is arranged electrically parallel with said conduction region of said layer of semiconductor material;

the resistance of said conduction region being greater than the resistance of said conductive resistor layer.

10. The integrated circuit of claim 9 further comprising a diffusion region of said second conductivity type formed in said upper surface of said layer of semiconductor material to a predetermined depth and being located beneath said insulating layer such that the conduction region in said layer of semiconductor material is reduced.

11. The integrated circuit of claim 9 further comprising another body region of said second conductivity type formed in said upper surface of said layer of semiconductor material and disposed between said body region and said drain diffusion region.

12. The integrated circuit of claim 11 further comprising a further metal contact disposed atop at least a portion of said another body region.

13. The integrated circuit of claim 12 wherein said further metal contact is electrically connected to said source electrode.

14. The integrated circuit of claim 11 further comprising a resurf region of said second conductivity type formed in said upper surface of said layer of semiconductor material and disposed between said another body region and said drain diffusion region and in contact with said another body region.

15. The integrated circuit of claim 9 wherein said source contact electrode further contacts a portion of said body region.

16. The integrated circuit of claim 9 further comprising a heavily doped spacer region of said second conductivity type formed in said layer of semiconductor material and extending into the substrate for electrically isolating said device.

17. A device for electrically coupling a floating voltage circuit with a relatively lower voltage circuit each formed in a common substrate with said MOSFET device, said MOSFET device comprising:

a layer of semiconductor material of first conductivity type disposed atop said substrate and being lightly doped and having an upper surface;

a source diffusion region of said second conductivity type opposite to that of said first conductivity type and formed in said upper surface of said layer of semiconductor material;

a source electrode connected to said source region and electrically coupled to said floating voltage circuit;

a gate insulation layer disposed over a portion of said upper surface of said layer of semiconductor material adjacent to said source diffusion region;

a conductive gate layer disposed over said gate insulation layer;

a drain region of said second conductivity type formed in said upper surface of said layer of semiconductor material and being laterally spaced away from said source diffusion region;

a drain electrode disposed atop said drain diffusion and electrically coupled to said lower voltage circuit;

a sinker region of said second conductivity type extending from said upper surface of said layer of semiconductor material and extending into said substrate and being laterally spaced away from said drain region and being further spaced away from said source diffusion;

a ground electrode connected to said sinker region;

an insulating layer disposed atop said upper surface of said layer of semiconductor material between said drain electrode and said ground electrode; and

a conductive resistor layer disposed atop said insulating layer and being connected between said ground electrode and said drain electrode.

18. The device of claim 17 further comprising an isolation diffusion region of said second conductivity type formed in said upper surface of said layer of semiconductor material and contacting said sinker region beneath said insulating layer and being laterally spaced away from said drain region to reduce parasitic resistances.

19. The device of claim 17 further comprising a lightly doped resurf region formed in said upper surface of said layer of semiconductor material in contact with said drain region and being arranged between said drain region and said source diffusion region.

20. The device of claim 17 further comprising a further diffusion region of said first conductivity type formed in said upper surface of said layer of semiconductor material and contacting said source diffusion region and said source electrode.

21. The device of claim 17 wherein at least one gap is formed in said sinker diffusion region.

22. An integrated circuit comprising:

a floating voltage circuit formed in a substrate;

a resurf diffusion region substantially surrounding said floating voltage circuit;

a relatively lower voltage circuit formed in said substrate; and

at least one level shift MOSFET device formed in said substrate and electrically coupled between said floating voltage circuit and said lower voltage circuit, said MOSFET device being formed in a gap in said resurf region;

said MOSFET device comprising;

a layer of semiconductor material of first conductivity type disposed atop said substrate and being lightly doped and having an upper surface;

a source diffusion region of said first conductivity type opposite to that of said first conductivity type and formed in said upper surface of said layer of semiconductor material;

a source electrode connected to said source region and electrically coupled to said floating voltage circuit;

a gate insulation layer disposed over a portion of said upper surface of said layer of semiconductor material adjacent to said source diffusion region;

a conductive gate layer disposed over said gate insulation layer;

a drain region of said second conductivity type formed in said upper surface of said layer of semiconductor material and being laterally spaced away from said source diffusion region;

a drain electrode disposed atop said drain diffusion and electrically coupled to said lower voltage circuit;

a sinker region of said second conductivity type extending from said upper surface of said layer of semiconductor material and extending into said substrate and being laterally spaced away from said drain region and being further spaced away from said source diffusion;

a ground electrode connected to said sinker region;

an insulating layer disposed atop said upper surface of said layer of semiconductor material and arranged between said drain electrode and said ground electrode; and

a conductive resistor layer disposed atop said insulating layer and being connected between said ground electrode and said drain electrode.

23. The integrated circuit of claim 22 further comprising an isolation diffusion region of said second conductivity type formed in said upper surface of said layer of semiconductor material and contacting said sinker region beneath said insulating layer and being laterally spaced away from said drain region to reduce parasitic resistances.

24. The integrated circuit of claim 22 further comprising a lightly doped resurf region formed in said upper surface of said layer of semiconductor material in contact with said drain region and being arranged between said drain region and said source diffusion region.

25. The integrated circuit of claim 22 further comprising a further diffusion region of said first conductivity type formed in said upper surface of said layer of semiconductor material and contacting said source diffusion region and said source electrode.

26. An integrated circuit comprising:

a floating voltage circuit formed in a substrate;

a resurf diffusion region enclosing said high voltage circuit;

a relatively lower voltage circuit formed in said substrate; and

at least one level shift MOSFET device formed in said substrate and electrically coupled between said high voltage circuit and said low voltage circuit, said resurf region at least partially enclosing said level shift MOSFET device and disposed between said level shift MOSFET device and said floating voltage device;

said MOSFET device comprising;

a layer of semiconductor material of first conductivity type disposed atop said substrate and being lightly doped and having an upper surface;

a source diffusion region of said first conductivity type opposite to that of said first conductivity type formed in said upper surface of said layer of semiconductor material;

a source electrode connected to said source region and electrically coupled to said floating voltage circuit;

a gate insulation layer disposed over a portion of said upper surface of said layer of semiconductor material adjacent to said source diffusion region;

a conductive gate layer disposed over said gate insulation layer;

a drain region of a second conductivity type formed in said upper surface of said layer of semiconductor material and being laterally spaced away from said source diffusion region;

a drain electrode disposed atop said drain diffusion and electrically coupled to said lower voltage circuit;

a sinker region of said second conductivity type extending from said upper surface of said layer of semiconductor material and extending into said substrate and being laterally spaced away from said drain region and being further spaced away from said source diffusion;

a ground electrode connected to said sinker region;

an insulating layer disposed atop said upper surface of said layer of semiconductor material and arranged between said drain electrode and said ground electrode; and

a conductive resistor layer disposed atop said insulating layer and being connected between said ground electrode and said drain electrode.

27. The integrated circuit of claim 26 further comprising a further diffusion region of said second conductivity type formed in said upper surface of said layer of semiconductor material and disposed between and contacting said resurf region and said drain region.

28. The integrated circuit of claim 26 further comprising a lightly doped resurf region formed in said upper surface of said layer of semiconductor material in contact with said drain region and being arranged between said drain region and said source diffusion region.

29. The integrated circuit of claim 26 further comprising a further diffusion region of said first conductivity type formed in said upper surface of said layer of semiconductor material and contacting said source diffusion region and said source electrode.

30. The integrated circuit of claim 26 further comprising a further conductive resistor layer connected between said drain electrode and said ground electrode in parallel with said conductive resistor layer.

31. A level shift device for electrically coupling a floating voltage circuit with a relatively lower voltage circuit each formed on a common substrate of semiconductor material with said level shift circuit, said level shift circuit comprising:

a layer of semiconductor material disposed atop said substrate, said semiconductor material being of a first conductivity type and being lightly doped and having an upper surface;

a base region of a second conductivity type opposite to that of said first conductivity type, said base region extending into the upper surface of said layer of semiconductor material to a given depth and having a substantially semicircular configuration;

a source region of said first conductivity type formed in said base region and defining a surface channel region between said source region and said layer of semiconductor material;

a source electrode connected to said source region and electrically coupled to said lower voltage circuit;

a gate insulation layer disposed over said channel region;

a conductive gate layer disposed over said gate insulation layer;

a drain electrode connected to a portion of said layer of semiconductor material thereby defining a drain region, said drain electrode being laterally spaced away from said base region;

a contact electrode connected to another portion of said layer of semiconductor material and electrically coupled to said floating voltage circuit, the portion of said layer of semiconductor material located between said drain electrode and said contact electrode defining a conduction region; and

a resistor disposed between said drain electrode and said contact electrode, said resistor being arranged electrically parallel with said conduction region of said layer of semiconductor material.

32. The device of claim 31 wherein said resistor comprises a diffusion region of said second conductivity type formed in said upper surface of said layer of semiconductor material to a predetermined depth.

33. The device of claim 31 further comprising another substantially semicircular body region of said second conductivity type formed in said upper surface of said layer of semiconductor material concentric with said body region and disposed between said body region and said drain electrode.

34. The device of claim 33 further comprising a further metal contact disposed atop at least a portion of said another body region.

35. The device of claim 34 wherein said further metal contact is electrically connected to said source electrode.

36. The device of claim 33 further comprising a resurf region of said second conductivity type formed in said upper surface of said layer of semiconductor material and disposed between said another body region and said drain diffusion region and in contact with said another body region.

37. The device of claim 31 wherein said resistor is a conducting layer disposed atop an insulating layer.

38. The device of claim 31 further comprising a heavily doped spacer region of said second conductivity type formed in said layer of semiconductor material and extending into the substrate for electrically isolating said device.

39. An integrated circuit comprising:

a floating voltage circuit;

a relatively lower voltage circuit; and

a level shift device formed in a common substrate with said floating voltage circuit and said lower voltage circuit and comprising;

a layer of semiconductor material disposed atop said substrate, said semiconductor material being of a first conductivity type and being lightly doped and having an upper surface;

a base region of a second conductivity type opposite to that of said first conductivity type, said base region extending into the upper surface of said layer of semiconductor material to a given depth and having a substantially semicircular configuration;

a source region of said first conductivity type formed in said base region and defining a surface channel region between said source region and said layer of semiconductor material;

a source electrode connected to said source region and electrically coupled to said lower voltage circuit;

a gate insulation layer disposed over said channel region;

a conductive gate layer disposed over said gate insulation layer;

a drain electrode connected to a portion of said layer of semiconductor material thereby defining a drain region;

said drain electrode being laterally spaced away from said base region;

a drain electrode connected to said drain contact diffusion region;

a contact electrode connected to another portion of said layer of semiconductor material and electrically coupled to said floating voltage circuit, the portion of said layer of semiconductor material located between said base region and said further diffusion region defining a conduction region; and

a resistor disposed between said drain electrode and said contact electrode, said resistor being arranged electrically parallel with said conduction region of said layer of semiconductor material.

40. The integrated circuit of claim 39 wherein said resistor comprises a diffusion region of said second conductivity type formed in said upper surface of said layer of semiconductor material to a predetermined depth.

41. The integrated circuit of claim 39, further comprising another substantially semicircular body region of said second conductivity type formed in said upper surface of said layer of semiconductor material concentric with said body region and disposed between said body region and said drain electrode.

42. The integrated circuit of claim 41 further comprising a further metal contact disposed atop at least a portion of said another body region.

43. The integrated circuit of claim 42 wherein said further metal contact is electrically connected to said source electrode.

44. The integrated circuit of claim 41 further comprising a resurf region of said second conductivity type formed in said upper surface of said layer of semiconductor material and disposed between said another body region and said drain diffusion region and in contact with said another body region.

45. The integrated circuit of claim 39 wherein said resistor is a conducting layer disposed atop an insulating layer.

46. The integrated circuit of claim 39 further comprising a heavily doped spacer region of said second conductivity type formed in said layer of semiconductor material and extending into the substrate for electrically isolating said device.

47. A device for electrically coupling a floating voltage circuit with a relatively lower voltage circuit each formed in a common substrate with said MOSFET device, said MOSFET device comprising:

a layer of semiconductor material of first conductivity type disposed atop said substrate and being lightly doped and having an upper surface;

a source diffusion region of said second conductivity type opposite to that of said first conductivity type and formed in said upper surface of said layer of semiconductor material;

a source electrode connected to said source region and electrically coupled to said floating voltage circuit;

a gate insulation layer disposed over a portion of said upper surface of said layer of semiconductor material adjacent to said source diffusion region;

a conductive gate layer disposed over said gate insulation layer;

a drain region of said second conductivity type formed in said upper surface of said layer of semiconductor material and being laterally spaced away from said source diffusion region;

a drain electrode disposed atop said drain diffusion and electrically coupled to said lower voltage circuit; and

a resistor connected between said ground electrode and said drain electrode.

48. The device of claim 47 further comprising a sinker region of said second conductivity type extending from said upper surface of said layer of semiconductor material and extending into said substrate and being laterally spaced away from said drain region and being further spaced away from said source diffusion;

and

a ground electrode connected to said sinker region.

49. The device of claim 48 further comprising an isolation diffusion region of said second conductivity type formed in said upper surface of said layer of semiconductor material and contacting said sinker region and being laterally spaced away from said drain region to reduce parasitic resistances.

50. The device of claim 47 further comprising a lightly doped resurf region formed in said upper surface of said layer of semiconductor material in contact with said drain region and being arranged between said drain region and said source diffusion region.

51. The device of claim 47 further comprising a further diffusion region of said first conductivity type formed in said upper surface of said layer of semiconductor material and contacting said source diffusion region and said source electrode.

52. An integrated circuit comprising:

a floating voltage circuit formed in a substrate;

a resurf diffusion region substantially surrounding said floating voltage circuit;

a relatively lower voltage circuit formed in said substrate; and

at least one level shift MOSFET device formed in said substrate and electrically coupled between said floating voltage circuit and said lower voltage circuit, said MOSFET device being formed in a gap in said resurf region;

said MOSFET device comprising;

a layer of semiconductor material of first conductivity type disposed atop said substrate and being lightly doped and having an upper surface;

a source diffusion region of said first conductivity type opposite to that of said first conductivity type and formed in said upper surface of said layer of semiconductor material;

a source electrode connected to said source region and electrically coupled to said floating voltage circuit;

a gate insulation layer disposed over a portion of said upper surface of said layer of semiconductor material adjacent to said source diffusion region;

a conductive gate layer disposed over said gate insulation layer;

a drain region of said second conductivity type formed in said upper surface of said layer of semiconductor material and being laterally spaced away from said source diffusion region;

a drain electrode disposed atop said drain diffusion and electrically coupled to said lower voltage circuit; and

a resistor connected between said ground electrode and said drain electrode.

53. The integrated circuit of claim 52 further comprising a sinker region of said second conductivity type extending from said upper surface of said layer of semiconductor material and extending into said substrate and being laterally spaced away from said drain region and being further spaced away from said source diffusion;

and

a ground electrode connected to said sinker region.

54. The integrated circuit of claim 53 further comprising an isolation diffusion region of said second conductivity type formed in said upper surface of said layer of semiconductor material and contacting said sinker region beneath said insulating layer and being laterally spaced away from said drain region to reduce parasitic resistances.

55. The integrated circuit of claim 52 further comprising a lightly doped resurf region formed in said upper surface of said layer of semiconductor material in contact with said drain region and being arranged between said drain region and said source diffusion region.

56. The integrated circuit of claim 52 further comprising a further diffusion region of said first conductivity type formed in said upper surface of said layer of semiconductor material and contacting said source diffusion region and said source electrode.

57. A device for electrically coupling a floating voltage circuit with a relatively lower voltage circuit each formed in a common substrate with said MOSFET device, said MOSFET device comprising:

a layer of semiconductor material of first conductivity type disposed atop said substrate and being lightly doped and having an upper surface;

a source diffusion region of said second conductivity type opposite to that of said first conductivity type, said source diffusion region being formed in said upper surface of said layer of semiconductor material and having a substantially semicircular configuration;

a source electrode connected to said source region and electrically coupled to said floating voltage circuit;

a gate insulation layer disposed over a portion of said upper surface of said layer of semiconductor material adjacent to said source diffusion region;

a conductive gate layer disposed over said gate insulation layer;

a drain region of said second conductivity type formed in said upper surface of said layer of semiconductor material and being laterally spaced away from said source diffusion region;

a drain electrode disposed atop said drain diffusion and electrically coupled to said lower voltage circuit; and

a resistor connected between said ground electrode and said drain electrode.

58. The device of claim 57 further comprising a sinker region of said second conductivity type extending from said upper surface of said layer of semiconductor material and extending into said substrate and being laterally spaced away from said drain region and being further spaced away from said source diffusion;

and

a ground electrode connected to said sinker region.

59. The device of claim 58 further comprising an isolation diffusion region of said second conductivity type formed in said upper surface of said layer of semiconductor material and contacting said sinker region and said drain region.

60. The device of claim 57 further comprising a lightly doped resurf region formed in said upper surface of said layer of semiconductor material in contact with said drain region and being arranged between said drain region and said source diffusion region.

61. The device of claim 57 further comprising a further diffusion region of said first conductivity type formed in said upper surface of said layer of semiconductor material and contacting said source diffusion region and said source electrode.

62. An integrated circuit comprising:

a floating voltage circuit formed in a substrate;

a resurf diffusion region enclosing said high voltage circuit;

a relatively lower voltage circuit formed in said substrate; and

at least one level shift MOSFET device formed in said substrate and electrically coupled between said high voltage circuit and said low voltage circuit, said resurf region at least partially enclosing said level shift MOSFET device and disposed between said level shift MOSFET device and said floating voltage device;

said MOSFET device comprising;

a layer of semiconductor material of first conductivity type disposed atop said substrate and being lightly doped and having an upper surface;

a source diffusion region of said first conductivity type opposite to that of said first conductivity type, said source diffusion region being formed in said upper surface of said layer of semiconductor material and having a substantially semicircular configuration;

a source electrode connected to said source region and electrically coupled to said floating voltage circuit;

a gate insulation layer disposed over a portion of said upper surface of said layer of semiconductor material adjacent to said source diffusion region;

a conductive gate layer disposed over said gate insulation layer;

a drain region of a second conductivity type formed in said upper surface of said layer of semiconductor material and being laterally spaced away from said source diffusion region;

a drain electrode disposed atop said drain diffusion and electrically coupled to said lower voltage circuit; and

a resistor connected between said ground electrode and said drain electrode.

63. The integrated circuit of claim 62 further comprising a sinker region of said second conductivity type extending from said upper surface of said layer of semiconductor material and extending into said substrate and being laterally spaced away from said drain region and being further spaced away from said source diffusion;

and

a ground electrode connected to said sinker region.

64. The integrated circuit of claim 63 further comprising a further diffusion region of said second conductivity type formed in said upper surface of said layer of semiconductor material and disposed between and contacting said resurf region and said drain region.

65. The integrated circuit of claim 62 further comprising a lightly doped resurf region formed in said upper surface of said layer of semiconductor material in contact with said drain region and being arranged between said drain region and said source diffusion region.

66. The integrated circuit of claim 62 further comprising a further diffusion region of said first conductivity type formed in said upper surface of said layer of semiconductor material and contacting said source diffusion region and said source electrode.

67. The integrated circuit of claim 64 wherein said further diffusion region comprises a further conductive resistor connected between said drain electrode and said ground electrode in parallel with said conductive resistor layer.