Integrated circuit layout

• US 5,801,959 A
• Filed: 09/12/1996
• Issued: 09/01/1998
• Est. Priority Date: 02/07/1995
• Status: Expired due to Fees

• Current Assignee: Silicon Valley Research Incorporated
• Original Assignee: Silicon Valley Research Incorporated
• Inventors: Zhu, Jiabi J., Ding, Cheng-Liang
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): PHAN, THAI Q
• Application Number:
  US08/713,597
• Time in Patent Office: 719 Days
• Field of Search: 364/489, 364/490, 364/491
• US Class Current: 716/119
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

The invention quickly produces a dense layout for an integrated circuit that enables a smaller die to be used to implement the integrated circuit than would otherwise be the case, resulting in a desirable size reduction in the final packaged integrated circuit. The invention combines routing space estimation and adjustment (a technique similar to channel-based global routing) with area-based detailed routing, resulting in an approach that provides the benefits of both channel-based and area-based layout techniques while minimizing the disadvantages of those techniques.

Claims

1. A method for determining an integrated circuit layout on a surface of a semiconductor die, the integrated circuit including a plurality of components, at least two of the components including at least one pin, the type and structure of the components and the interconnections between pins of various components being predefined, the method comprising the steps of:

determining a first component placement on the die surface, wherein;

each component is represented as a block or one of a plurality of cells in a row of cells;

a distance between adjacent cells within a row defines a cell spacing; and

a region between defined locations of adjacent blocks and/or cell rows defines a channel having a channel height; and

routing each interconnection, the step of routing further comprising the steps of;

performing routing space estimation and adjustment to approximately define the routing demand, wherein, after the routing space estimation and adjustment step, the area of the die surface, each channel height and each cell spacing have a particular magnitude that together define a second component placement; and

performing area-based detailed routing to exactly define the path of each interconnection, the magnitude of the die surface area after the detailed routing step remaining unchanged from the magnitude of the die surface area before the detailed routing step.

2. A method as in claim 1, wherein the step of performing routing space estimation and adjustment further comprises the step of adjusting one or more channel heights.

3. A method as in claim 1, wherein the step of performing routing space estimation and adjustment further comprises the step of performing gridded channel-based global routing.

4. A method as in claim 1, wherein the step of performing routing space estimation and adjustment further comprises the step of performing gridless channel-based global routing.

5. A method as in claim 1, wherein only the second component placement, interconnections between pins and the magnitude of the die surface area after the routing space estimation and adjustment step are supplied as input information for the area-based detailed routing step.

6. A method as in claim 1, wherein the approximate paths of the interconnections are supplied from the routing space estimation and adjustment step as input information for the area-based detailed routing step.

7. A method as in claim 1, further comprising, after the steps of performing routing space estimation and adjustment and area-based detailed routing, iteratively performing the steps of:

changing the magnitude of the area of the die surface; and

performing a subsequent area-based detailed routing to exactly define the path of each interconnection on the die surface, the results of the subsequent step of performing area-based detailed routing replacing the results of the previous step of performing area-based detailed routing.

8. A method as in claim 7, further comprising, before a subsequent step of performing area-based detailed routing, the step of changing one or more channel heights.

9. A method as in claim 8, further comprising, before a subsequent step of performing area-based detailed routing, the step of changing one or more cell spacings.

10. A method as in claim 7, further comprising, before a subsequent step of performing area-based detailed routing, the step of changing one or more cell spacings.

11. A method as in claim 1, further comprising, after the steps of performing routing space estimation and adjustment and area-based detailed routing, iteratively performing the steps of:

changing one or more channel heights; and

performing a subsequent area-based detailed routing to exactly define the path of each interconnection on the die surface, the results of the subsequent step of performing area-based detailed routing replacing the results of the previous step of performing area-based detailed routing.

12. A method as in claim 11, further comprising, before a subsequent step of performing area-based detailed routing, the step of changing one or more cell spacings.

13. A method as in claim 1, further comprising, after the steps of performing routing space estimation and adjustment and area-based detailed routing, iteratively performing the steps of:

changing one or more cell spacings; and

performing a subsequent area-based detailed routing to exactly define the path of each interconnection on the die surface, the results of the subsequent step of performing area-based detailed routing replacing the results of the previous step of performing area-based detailed routing.

14. A method as in claim 1, wherein the step of performing routing space estimation and adjustment further comprises the steps of:

defining the location of one or more vertices for each channel;

assigning each pin to a vertex; and

routing each interconnection between the vertices associated with the pins being interconnected.

15. A method as in claim 14, wherein the step of routing each interconnection between the vertices further comprises maze routing.

16. A method as in claim 14, wherein the step of routing each interconnection between the vertices further comprises line-probe routing.

17. A method as in claim 1, wherein the step of performing routing space estimation and adjustment further comprises the steps of:

dividing the die surface into a plurality of rectangles;

assigning each pin to a rectangle; and

routing each interconnection between the rectangles associated with the pins being interconnected.

18. A method as in claim 17, wherein the step of routing each interconnection between the rectangles further comprises maze routing.

19. A method as in claim 1, further comprising, after the step of performing routing space estimation and adjustment, the steps of:

determining, for each component, whether the component is at a location that enables interconnection to be made to the pin or pins of the component; and

for each component that is not at such a location, relocating the component to a location that enables interconnection to be made to the pin or pins of the component.

20. A method as in claim 19, wherein:

the step of determining further comprises the steps of;

defining a routing grid; and

evaluating at least one pin of each component to determine whether the pin is located on an intersection of the routing grid; and

the step of relocating further comprises the step of moving the component such that at least one pin of the component is located on an intersection of the routing grid.

21. A method as in claim 19, wherein:

the step of determining further comprises the steps of;

defining a routing grid and a placement grid; and

evaluating a defined point of each component to determine whether the defined point is located on an intersection of the placement grid; and

the step of relocating further comprises the step of moving the component such that the defined point is located on an intersection of the placement grid.

22. A method as in claim 19, further comprising, after the steps of performing routing space estimation and adjustment and area-based detailed routing, iteratively performing the steps of:

changing the magnitude of the area of the die surface such that the component placement is changed; and

determining, for each component, whether the component is at a location that enables interconnection to be made to the pin or pins of the component;

for each component that is not at such a location, relocating the component to a location that enables interconnection to be made to the pin or pins of the component; and

performing a subsequent area-based detailed routing to exactly define the path of each interconnection on the die surface, the results of the subsequent step of performing area-based detailed routing replacing the results of the previous step of performing area-based detailed routing.

23. A method as in claim 1, further comprising, after the step of performing routing space estimation and adjustment, the step of changing the magnitude of the die surface area, if necessary, to have a predetermined magnitude, the step of changing the magnitude of the die surface area further comprising the step of relocating each component so as to maintain the same proportional relationship between the magnitudes of the cell spacings and the channel heights before and after the step of changing the magnitude of the die surface area.

24. A method as in claim 23, further comprising, after the step of changing the magnitude of the die surface area, the steps of:

determining, for each component, whether the component is at a location that enables interconnection to be made to the pin or pins of the component; and

for each component that is not at such a location, relocating the component to a location that enables interconnection to be made to the pin or pins of the component.

25. A method as in claim 23, further comprising, after the step of changing the magnitude of the die surface area, the step of relocating each input cell or pin and output cell or pin to a predefined location.

26. A method as in claim 25, further comprising, after the step of relocating each input cell or pin and output cell or pin to a predefined location, the steps of:

determining, for each component, whether the component is at a location that enables interconnection to be made to the pin or pins of the component; and

for each component that is not at such a location, relocating the component to a location that enables interconnection to be made to the pin or pins of the component.

27. A method as in claim 1, wherein the step of performing routing space estimation and adjustment further comprises the step of adjusting one or more cell spacings.

28. A system for determining an integrated circuit layout on a surface of a semiconductor die, the integrated circuit including a plurality of components, at least two of the components including at least one pin, the type and structure of the components and the interconnections between pins of various components being predefined, the system comprising:

means for determining a first component placement on the die surface, wherein;

each component is represented as a block or one of a plurality of cells in a row of cells;

a distance between adjacent cells within a row defines a cell spacing; and

a region between defined locations of adjacent blocks and/or cell rows defines a channel having a channel height; and

means for routing each interconnection, the means for routing further comprising;

means for performing routing space estimation and adjustment to approximately define the routing demand, the performance of routing space estimation and adjustment resulting in the determination of a particular magnitude for the area of the die surface, each channel height and each cell spacing that together define a second component placement; and

means for performing area-based detailed routing to exactly define the path of each interconnection, the magnitude of the die surface area after the detailed routing remaining unchanged from the magnitude of the die surface area before the detailed routing.