Memory system having programmable control parameters

• US 5,801,985 A
• Filed: 07/28/1995
• Issued: 09/01/1998
• Est. Priority Date: 07/28/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F., Chevallier, Christophe J., Briner, Michael S., Rinerson, Darrell D.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/508,828
• Time in Patent Office: 1,131 Days
• Field of Search: 365/201, 365/189.01, 365/185.01, 365/185.02, 365/189.02, 365/185.24, 365/185.33
• US Class Current: 365/185.01
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits

Abstract

A memory system capable of being configured for optimum performance after fabrication using control parameters stored in non-volatile data storage units. The system includes an array of memory cells, separate from the data storage units, arranged in a multiplicity of rows and a multiplicity of columns, with each cell located in one of the rows being coupled to a common word line and with each cell located in one of the columns being coupled to a common bit line. Control circuitry for controlling memory operations such as programming the memory cells and reading the memory cells when the memory system is in a normal mode of operation. The non-volatile data storage units store control parameter data used by the control means for controlling the memory operations, with the control parameters being modifiable when the memory system is placed in an alternative mode of operation as opposed the normal mode of operation. Once the memory has been fabricated and characterized, the control parameters can be selected for optimum memory performance and loaded into the data storage units.

Claims

1. A memory system comprising:

an array of memory cells arranged in a multiplicity of rows and a multiplicity of columns, with each cell located in one of the rows and one of the columns;

a memory controller, operably coupled to the array, said memory controller configured to control memory operations, with the memory operations comprising memory programming operations wherein the memory cells are programmed and memory reading operation wherein the memory cells are read;

a plurality of non-volatile data storage units, with the data storage units storing control parameter data used by the memory controller to control the memory operations; and

switching mode circuitry configured to switch the memory system between a normal operating mode wherein the cells of the array may be programmed and read and an alternative operating mode wherein the control parameter data in the data storage units can be either modified or accessed.

2. The memory system of claim 1 wherein the memory controller comprises circuitry configured to apply voltage pulses to the array of memory cells, with the voltage pulses having a duration and magnitude and wherein the duration of the voltage pulses can be altered based upon duration control parameter data stored in the data storage units.

3. The memory system of claim 2 wherein the magnitude of the voltage pulses can be altered based upon magnitude control parameter data stored in the data storage units.

4. The memory system of claim 1 wherein the memory controller comprises circuitry configured to apply voltage pulses to the array of memory cells, with the voltage pulses having a duration and magnitude and wherein the magnitude of the voltage pulses can be altered based upon magnitude control parameter data stored in the data storage units.

5. The memory system of claim 4 wherein the duration of the voltage pulses can be altered based upon duration control parameters stored in the data storage units.

6. The memory system of claim 1 wherein the memory operations comprise memory erase operations wherein the memory cells are erased and the voltage pulses include erase voltage pulses.

7. The memory system of claim 1 wherein the memory system outputs a word of data in the memory read operations and inputs a word of data in the memory program operations, with the word of data having a variable number of bits and the memory controller comprises circuitry configured to vary the number of bits in the word based upon word control parameters stored in the data storage units.

8. The memory system of claim 1 wherein the memory system comprises circuitry configured to address the array of memory cells using a memory address, with the memory address corresponding to a portion of the array and wherein the memory controller comprises circuitry configured to vary the portion of the array which corresponds to the address based upon address control parameters stored in the data storage units.

9. The memory system of claim 1 wherein the memory system comprises sense amplifiers configured to compare output voltages indicative of current flow through the memory cells with a reference voltage and wherein the memory controller comprises circuitry configured to vary a magnitude of the reference voltage based upon reference control parameters stored in the data storage units.

10. The memory system of claim 1 wherein the memory cells are flash memory cells and the data storage units comprise a flash memory cell for storing the control parameter data.

11. The memory system of claim 10 wherein the data storage units comprise a volatile data latch coupled to the flash memory cell and wherein the volatile data latch is loaded with control parameter data from the flash cell of the data storage unit when power is first applied to the memory system.

12. The memory system of claim 11 wherein the control parameter data in the data storage units is modified by transferring control parameter data to the volatile data latch of a data storage unit and then transferring the control parameter data from the volatile data latch of the storage unit to the flash cell of the storage unit.

13. A memory system comprising:

an array of memory cells arranged in a multiplicity of rows and a multiplicity of columns, with each cell located in one of the rows being coupled to a common word line and with each cell located in one of the columns being coupled to a common bit line;

a memory controller, operably coupled to the array said memory controller configured to control memory operations, with the memory operations comprising programming operations to program the memory cells and reading operations to read the memory cells;

a plurality of non-volatile data storage units, with the data storage units storing control parameter data used by the memory controller to control the memory operations; and

modification circuitry, operably coupled to the data storage units, the modification circuitry configured to modify the control parameter data so as to alter the memory operations.

14. The memory system of claim 13 wherein the memory system outputs a word of data in the read operations and inputs a word of data in program operations and wherein the memory controller comprises

circuitry configured to apply voltage pulses to the array of memory cells, with the voltage pulses having a duration and a magnitude;

circuitry configured to address the array of memory cells using a memory address, with the memory address corresponding to a portion of the array;

sense amplifiers configured to compare output voltages indicative of current flow through the memory cells with a reference voltage; and

wherein the memory controller further comprises at least one of the following four types of circuitry

(1) circuitry configured to vary the number of bits in the word based upon word control parameters stored in the data storage units;

(2) circuitry configured to vary the duration of the voltage pulses based upon duration control parameters stored in the data storage units;

(3) circuitry configured to vary the magnitude of the voltage pulses based upon magnitude control parameters stored in the data storage units;

(4) circuitry configured to vary a magnitude of the reference voltage based upon reference control parameters stored in the data storage units.

15. The memory system of claim 14 wherein the memory controller comprises at least two of the circuitry types.

16. The memory system of claim 14 wherein the memory controller comprises at least three of the circuitry types.

17. The memory system of claim 14 wherein the memory controller comprises all four of the circuitry types.

18. A memory system comprising:

an array of memory cells arranged in a multiplicity of rows and columns;

a memory controller, operably coupled to the array of memory cells, configured to control reading and programming operations on the array of memory cells, with the reading and programming operations being controlled in response to control parameters;

a data storage structure, operably coupled to the memory controller, said data storage structure configured to store the control parameters; and

switching mode circuitry configured to switch the memory system between a normal operating mode wherein the memory reading and programming operations can be carried out and an alternative operating mode wherein the control parameters stored in the data storage structure can be altered.

19. The memory system of claim 18 further comprising memory terminals for providing an interface between the memory system and an environment external to the memory system, with the terminals having a normal function when the memory is in the normal operating mode and an alterative function when the memory is in the alternative operating mode, with one of the alternative functions being the function of receiving control parameter data to be stored in the data storage structure.

20. The memory system of claim 19 wherein the memory terminals including a first group of the terminals that provide a memory address function in the normal operating mode and that provide the function of receiving control parameter data in the alternative operating mode.

21. The memory system of claim 19 wherein data storage structure includes data storage units for storing the control parameters, with the data storage units having inputs configured to receive the control parameter data at the memory terminals only when the memory system is in the alternative operating mode.

22. The memory system of claim 21 wherein control parameters stored in the data storage units can be read using the memory terminals when the memory system is in the alternative operating mode.

23. The memory system of claim 22 wherein the control parameters stored in the data storage structure are divided into major groups of control parameters and wherein one of the major groups of control parameters can be selected to be read by applying a major group select signal to one of the memory terminals when the memory system is in the alternative operating mode.

24. The memory system of claim 22 wherein the memory controller carries out memory program operations by applying voltage pulses to the array of memory cells and wherein a first one of the major groups of control parameters controls a duration of the memory pulses and a second one of the major groups of control parameters controls a magnitude of the program pulses.

25. The memory system of claim 24 wherein further comprising sense amplifier circuitry, operably coupled to the array of memory cells, configured to sense memory cell current in the reading operations and wherein a third one of the major groups of control parameters controls operation of the sense amplifier circuitry.

26. The memory system of claim 25 wherein the major group select signal comprises signals applied to two of the memory terminals.

34. The memory system of claim 18 wherein the memory controller is further configured to control erasing operations on the array of memory cells, with the memory programming and erasing operations being carried out by applying voltage pulses to the array of memory cells and wherein the memory controller controls magnitude and pulse widths of the applied voltage pulses in response to the stored control parameters.

27. The memory system of claim 27 wherein the data storage structure comprises an individual data storage unit configured to store each of the control parameters and a comparator circuit associated with each of the data storage units, with the comparator circuit operably coupled to the associated data storage unit and one of the memory terminals and configured to provide a comparator output based upon a comparison of a state of the control parameter stored in the data storage unit and a state of a compare signal applied to the memory terminal when the memory system is in the alternative operating mode.

28. The memory system of claim 27 wherein the comparator outputs are operably coupled to a memory terminal when the memory system is in the alternative operating mode.

29. The memory system of claim 28 wherein the memory outputs are operably coupled to a single one of the memory terminals.

30. The memory system of claim 28 wherein the data storage structure is further configured so that the comparator outputs are combined into a single verify output which is indicative of a state of the comparator outputs.

31. The memory system of claim 30 wherein the storage structure is further configured to that the single verify signal is indicative of the comparator outputs of selected ones of the comparators.

32. The memory system of claim 31 wherein the selected ones of the comparators is selected based upon a select signal applied to the memory terminals when the memory system is in the alternative operating mode.

33. The memory system of claim 32 wherein the memory terminals operably coupled to the comparator circuits function as memory address terminals when the memory system is in the normal operating mode.

35. A flash memory system implemented in an integrated circuit, said memory system comprising:

a plurality of memory terminals for providing an interface between the integrated circuit and an environment external to the integrated circuit;

an array of flash memory cells arranged in a multiplicity of rows and columns;

a memory controller, operably coupled to the array of flash memory cells, said memory controller configured to carry out memory programming, erasing and reading operations in response to a plurality of control parameters;

a plurality of data storage units configured to store the control parameters;

mode control circuitry configured to switch the memory system between a normal operating mode where the memory programming, erasing and reading operations can be carried out and an alternative operating mode where the control parameters can be altered by way of the memory terminals.

36. The memory system of claim 35 wherein the memory programming and erasing operations are carried out by application of voltage pulses to the array of flash memory cells and wherein the control parameters function to vary magnitudes and durations of the voltage pulses.

37. The memory system of claim 36 further comprising control parameter verify circuitry operably coupled to the data storage units and the memory terminals, with the verify circuitry comprising a comparator circuit associated with each of the data storage units and configured to compare a state of the control parameter stored in the associated data storage unit with the state of a verify signal applied to the memory terminals when the memory system is in the alternative operating mode.

38. The memory system of claim 37 wherein the control parameters stored in the data storage units are divided into at least two major groups of control parameters and wherein the data storage units storing one of the major groups of control parameters can be selected to be verified by applying a major group select signals to at least two of the memory terminals when the memory system is in the alternative operating mode.

39. The memory system of claim 38 wherein the first major group of control parameters control the magnitudes of the voltage pulses and the second major group of control parameters control the duration of the voltage pulses.

40. The memory system of claim 39 further comprising sense amplifier circuitry, operably coupled to the array of flash memory cells, with the sense amplifier circuitry configured to sense cell current in the memory reading operation and wherein the major groups further comprise a third major group of control parameters that control the sense amplifier circuitry.

41. The memory system of claim 38 wherein at least one of the major groups of control parameters is divided into at least two minor groups of control parameters and wherein the data storage units storing one of the minor groups of control parameters can be selected to be verified by applying a minor group select signal to the memory terminals when the memory system is in the alternative operating mode.

42. The memory system of claim 41 wherein the array of flash memory cells comprises a plurality of word lines respectively coupled to the flash memory cells located in one of the rows of the array and comprises a plurality of bit lines respectively coupled to the flash memory cells located in one of the columns of the array and wherein the memory controller causes the voltage pulses to be applied to the word lines of the array and the voltage pulses to be applied to the bit lines of the array during the programming operations and wherein one of the minor groups of control parameters of the first major group of control parameters comprise control parameters used by the memory controller to control the magnitude of the voltage pulses applied to the array word lines in the memory programming operations and a second one of the minor group of control parameters of the first major group comprise control parameters used by the memory controller to control the magnitude of the voltage pulses applied to the array bit lines in the memory programming operations.

43. The memory system of claim 42 wherein the array includes a source line coupled to the cells of the array and wherein the memory controller applies voltage pulses to the source line during the memory erasing operation and wherein a third one of the minor group of control parameters of the first group of control parameters are used by the memory controller to control a magnitude of the voltage pulses applied to the source line.

44. The memory system of claim 41 wherein the major and minor groups of select signals are applied to memory terminals used as address terminals when the memory system is in the normal operating mode.

45. A method of controlling operation of a memory system having an array of memory cells arranged in a multiplicity of rows and columns, the method comprising the following steps:

placing the memory system to an alternative operating mode;

storing a plurality of control parameters in data storage units separate from the array of memory cells;

switching the memory system from the alternative operating mode to a normal operating mode; and

programming data into the array of memory cells using the stored control parameters.

46. The method of claim 45 wherein the step of programming data comprises the step of applying programming voltage pulses to the array of memory cells having a magnitude controlled by the stored control parameters.

47. The method of claim 46 wherein the step of programming data comprises the step of controlling a duration of the applied voltage pulses using the stored control parameters.

48. The method of claim 47 further comprising the steps of preventing the step of carrying out the programming data step when the memory system is placed in the alternative operating mode and preventing the step of carrying out the storing of the control parameters when the memory system is in the normal operating mode.

49. The method of claim 48 wherein the step of programming data includes the step of applying programming signals to a first group of memory system terminals and wherein the step of storing the control parameters includes the step of applying control parameter data to the first group of memory system terminals.

50. The method of claim 49 wherein the first group of memory system terminals function as address terminals during the step of programming data into the array.

51. The method of claim 45 further comprising the step of verifying the control parameters stored in the data storage units.

52. The method of claim 51 wherein the step of verifying comprises the step of applying test control parameter data to the memory system terminals and comparing the applied test control parameter data with the control parameters stored in the data storage units.

53. The method of claim 52 wherein the step of verifying further comprises the step of varying the applied test control parameter data if the applied test control parameter data does not match the stored control parameters during the step of comparing.

54. The method of claim 53 wherein the step of comparing includes the step of generating a compare signal indicative of whether there is a match between the applied test control parameter data and the stored control parameters.

55. The method of claim 53 where the step of comparing includes the step of applying the compare signal to a memory system terminal.

56. The method of claim 55 wherein the data storage units are divided into major groups and wherein the step of verifying includes the step of selecting one of the major groups of data storage units to be verified.

57. The method of claim 56 wherein the step of selecting a major group comprises the step of applying a major group select signal to a memory system terminal.

58. The method of claim 57 wherein the major groups of data storage units each comprise minor groups of data storage units and wherein the step of verifying includes the step of selecting one of the minor groups of data storage units to be verified.

59. The method of claim 58 wherein the step of selecting a minor group comprises the step of applying a minor group select signal to a memory system terminal.

60. The method of claim 59 further comprising the step of reading the array of memory cells when the memory system is switched to the normal operating mode using the stored control parameters.

61. The method of claim 60 wherein a first one of the major groups of data storage units comprises control parameters used to control the step of reading, a second one of the major groups comprises data storage units storing control parameters used to control the magnitude of the voltage pulses applied in the step of programming and a third one of the major groups include data storage units used to control the duration of the voltage pulses applied in the step of programming.

62. The method of claim 61 wherein the step of applying voltage pulses to the array during the step of programming comprises the application of voltage pulses to word lines of the array and the application of voltage pulses to bit lines of the array and wherein a first minor group of the first major group of the data storage units comprises data storage units that store control parameters that are used to control a magnitude of the programming pulses applied to the word lines of the array and a second minor group of the first major groups comprises data storage units that store control parameters that are used to control a magnitude of the programming pulses applied to the bit lines of the array.

63. A method of controlling operation of a memory system having an array of memory cells arranged into a multiplicity of rows and columns, said method comprising the following steps:

applying control parameter data to terminals of the memory system;

storing a plurality of control parameters in data storage units indicative of the applied control parameter data;

programming data into the array of memory cells using the stored control parameters;

reading data in the array of memory cells using the stored control parameters; and

erasing data in the array using the stored control parameters.

64. The method of claim 63 further comprising the step of modifying the stored control parameters using the terminals of the memory system.

65. The method of claim 64 further comprising the step of switching the memory between a normal operating mode wherein the steps of programming, reading and erasing can be carried out and the step of storing and modifying cannot be carried out and an alternative operating mode wherein the steps of storing and modifying can be carried out and the steps of programming, reading and erasing cannot be carried out.

66. The method of claim 65 wherein the memory system includes a group of memory system terminals used in the steps of programming and reading the array and wherein the group of memory system terminals are further used in the steps of storing and modifying.

67. The method of claim 64 wherein the step of programming the array comprises the step of applying voltage pulses to the array and wherein the control parameters are used to control duration and magnitude of the voltage pulses applied during programming.

68. The method of claim 67 wherein the step of erasing the array comprises the step of applying voltage pulses to the array and wherein the control parameters are used to control duration and magnitude of the voltage pulses applied during erasing.

69. The method of claim 68 wherein the step of reading the array comprises the step of sensing current flow through memory cells of the array and wherein the control parameters are used in the step of sensing.

70. The method of claim 69 wherein the control parameters are stored in a non-volatile data storage unit separate from the array of memory cells.