Nonvolatile memory device

• US 5,801,993 A
• Filed: 08/07/1997
• Issued: 09/01/1998
• Est. Priority Date: 10/01/1996
• Status: Expired due to Term

• Current Assignee: Fidelix Company Limited
• Original Assignee: LG Semico Company Limited (SK Hynix Inc.)
• Inventors: Choi, Woong Lim
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US08/911,373
• Time in Patent Office: 390 Days
• Field of Search: 365/185.21, 365/185.28, 365/185.29, 365/185.33, 365/218
• US Class Current: 365/185.28
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• CPC Class Codes: G11C 2211/5613 Multilevel memory cell with additional gates, not being floating or control gates

Abstract

A nonvolatile memory device includes a plurality of program/select lines arranged in a row direction spaced apart from each other in first prescribed intervals, a plurality of bit lines arranged in a column direction spaced apart from each other in second prescribed intervals at a substantially right angle to the plurality of the program/select lines to form a matrix of a plurality of square areas, and a plurality of control lines disposed in the column direction and adjacent to the bit lines in a one-to-one correspondence. Each cell is disposed in one of the square areas, and has a source, a drain, and a channel region. Further, a select/program gate of each cell allows the selection of the cell for programming and conducting the programming by means of charge carriers. A floating gate stores the charge carriers by means of tunneling through the channel region during erasure and provides the stored charge carriers to the program/select gate through the tunneling diode during programming. A control gate controls an amount of the charge carriers provided from the floating gate to the program/select gate. The program/select gates in the cells disposed in the same row are commonly connected to one of the program/select lines, and the control gates in the cells disposed in the same column are commonly connected to one of the control lines. The sources (or drains) in the cells disposed in the same row are commonly connected to one of the bit lines, together with the drains (or sources) of the cells disposed in an adjacent row.

Claims

1. A nonvolatile memory device comprising:

a plurality of program/select lines arranged in a row direction spaced apart from each other at first prescribed intervals;

a plurality of bit lines arranged in a column direction spaced apart from each other in second prescribed intervals to form a matrix of a plurality of square areas; and

a plurality of control lines disposed in the column direction and adjacent to the bit lines in a one-to-one correspondence;

a plurality of cells, each disposed in one of the square areas and including a source, a drain, a channel region, a select/program gate for selecting a cell for programming and conducting the programming by means of charge carriers, a floating gate for storing the charge carriers by means of tunneling through the channel region in erasure of a tunneling diode and providing the stored charge carriers to the program/select gate through the tunneling diode in programming, and a control gate for controlling an amount of the charge carriers provided from the floating gate to the program/select gate,

wherein the program/select gates in the cells disposed on the same row are connected to one of the program/select lines in common, the control gates in the cells disposed on the same column are connected to one of the control lines in common, and the sources(or drains) in the cells disposed on the same row are connected to one of the bit lines in common, together with one of the drains and sources of the cells disposed on an adjacent row.

2. A nonvolatile device of claim 1, wherein a first voltage of 10V is applied to selected program/select lines, a second voltage of 0V is applied to unselected program/select lines, a third voltage of -6V˜

-3V is applied to selected control gate lines, a fourth voltage of 5V is applied to unselected control gate lines, a fifth voltage of 1V is applied to a selected nth bit line BLn, a sixth voltage of 0V is applied to a selected (n-1)th bit line BLn-1, a seventh voltage of 1V is applied to one of unselected bit lines BLm (m≧

n+1), and an eighth voltage of 0V is applied to remaining unselected bit lines to operate the nonvolatile memory device in a program mode.

3. A nonvolatile memory device of claim 1, wherein a first voltage of -8V is applied to selected program/select lines, a second voltage of 0V is applied to unselected program/select lines, a third voltage of 8V is applied to selected control lines, a fourth voltage of 0V is applied to unselected control lines, and a fifth voltage of 0V is applied to the substrate and all the bit lines are floating to operate the nonvolatile memory device in a tunneling erasure mode using the program/select lines.

4. A nonvolatile memory device of claim 1, wherein a first voltage of 0V is applied to selected program/select lines, a second voltage of 0V is applied to unselected program/select lines, a third voltage of 10V is applied to selected control lines, a fourth voltage of 0V is applied to unselected control lines, a fifth voltage of -5V is applied to selected bit lines, and a sixth voltage of 0V is applied to the substrate, and unselected bit lines are floating such that the nonvolatile memory device operates in a tunneling erasure mode using the bit lines.

5. A nonvolatile Memory device of claim 1, wherein a first voltage of 5V is applied to selected program/select lines, a second voltage of 0V is applied to unselected program/select lines, a third voltage of 12V is applied to selected control lines, a fourth voltage of 0V is applied to unselected control lines, a fifth voltage of 7V is applied to selected bit lines, and a sixth voltage of 0V is applied to the substrate, and unselected bit lines are left floating such that the nonvolatile memory device operate in an erasure mode by hot carrier injection mechanism through the drains of selected memory cells.

6. A nonvolatile memory device of claim 1, wherein a first voltage of 2V is applied to selected program/select lines, a second voltage of 0V is applied to unselected program/select lines, a third voltage of 10V is applied to selected control lines, a fourth voltage of 0V is applied to unselected control lines, a fifth voltage of 5V is applied to selected bit lines, and a sixth voltage of 0V is applied to the substrate, and unselected bit lines are floating such that the nonvolatile memory device operates in an erasure mode by hot carrier injection mechanism through the sources of selected memory cells.

7. A nonvolatile memory device of claim 1, wherein a direct first voltage is applied to selected program/select lines, a second voltage of 0V is applied to unselected program/select lines, the first voltage is applied to selected control lines, a third voltage of 0V is applied to unselected control lines, a fourth voltage of 1V is applied to selected bit lines, a fifth voltage of 1V is applied to one of unselected bit lines BLm (m≧

n+1), and a sixth voltage of 0V is applied to remaining unselected bit lines BLm (m≧

n+1) to operate the nonvolatile memory device in a read mode.

8. A memory device comprising:

a) a plurality of bit lines arrange in a first direction;

b) a plurality of select lines in a second direction to form a matrix of predetermined areas;

c) a plurality of control lines in a third direction which is substantially parallel with one of said plurality of bit lines and said plurality of select lines;

d) a plurality of memory cells, each memory cell being disposed in each predetermined area defined by corresponding bit line and select line and including;

i) first and second electrodes and a channel region therebetween, said first electrode being coupled to a corresponding bit line and said second electrode coupled to one of said plurality of bit lines adjacent to the corresponding bit line;

ii) a first gate for storing a prescribed amount of charge carriers;

iii) a second gate, coupled to a corresponding select line, for selecting a memory cell for a prescribed operation; and

iv) a third gate, coupled to a corresponding control line, for inducing a transfer of charge carrier from said first gate to said second gate during programming operation, wherein

a first current path due to the transfer of charge carriers is separate from a second current path due to a current flowing between said first and second electrodes.

9. The memory device of claim 8, wherein

said first and second electrodes of each memory cell comprises first and second regions of a first conductivity type in a semiconductor substrate of a second conductivity type with channel region, corresponding to the channel being formed between the first and second regions;

said first gate being insulated and formed across a first portion of said channel region;

said second gate being insulated and formed across a second portion of said channel region, said second gate being adjacent to said first gate; and

said third gate being insulated and formed across said first gate, wherein charge carriers are transferred from said first gate to said second gate through an insulating film formed therebetween by at least one of hot carrier injection and tunneling.

10. The memory device of claim 8, wherein constant voltages are applied to said plurality of bit lines, control lines and select lines for a predetermined period of time for the prescribed operation.

11. The memory device of claim 8, wherein for programming a threshold voltage level of selected memory cell of said plurality of memory cells,

a first voltage is applied to the select line coupled to the selected memory cell;

a second voltage is applied to the control line coupled to the selected memory cell; and

a third voltage is applied to the bit line coupled to the first electrode of the selected memory cell and an unselected bit line, adjacent to the bit line coupled to the selected memory cell.

12. The memory device of claim 11, wherein the third voltage is greater than the second voltage and less than the first voltage.

13. The memory device of claim 11, wherein fourth voltage is applied to all unselected control lines, and a fifth voltage is applied to all remaining unselected select lines, a bit line coupled to the second electrode of the select memory cell and all remaining unselected bit lines.

14. The memory device of claim 13, wherein said first, second, third, fourth and fifth voltages are about 10V, -6˜

-3V, 1V, 5V and 0V, respectively.

15. The memory device of claim 8, wherein for operating selected memory cells of said plurality of memory cells in an erasure mode of the prescribed operation, a first voltage is applied to select lines coupled to said selected memory cells and a second voltage is applied to control lines coupled to said selected memory cells, all other control lines, bit lines and select lines being one of 0V and floating.

16. The memory device of claim 15, wherein the second voltage is greater than the first voltage.

17. The memory device of claim 16, wherein the first voltage is about -8V and the second voltage is about 8V.

18. The memory device of claim 8, wherein for operating selected memory cells of said plurality of memory cells in an erasure mode of the prescribed operation, a first voltage is applied to control lines coupled to said selected memory cells and a second voltage is applied to bit lines coupled to said selected memory cells, all other control lines, bit lines and select lines being one of 0V and floating.

19. The memory device of claim 18, wherein the second voltage is less than the first voltage.

20. The memory device of claim 19, wherein the first voltage is about 10V and the second voltage is about -5V.

21. The memory device of claim 8, wherein for operating selected memory cells of said plurality of memory cells in an erasure mode of the prescribed operation, first, second and third voltages are applied to select lines, control lines and bit lines, respectively, coupled to said selected memory cells and all other control lines, bit lines and select lines being one of 0V and floating.

22. The memory device of claim 21, wherein the third voltage is greater than the first voltage and less than the second voltage.

23. The memory device of claim 22, wherein the first, second and third voltages are about 5V, 12V and 7V, respectively.

24. The memory device of claim 22, wherein the first, second and third voltages are about 2V, 10V and 5V, respectively.

25. The memory device of claim 8, wherein for operating a selected memory cell of said plurality of memory cells in a read mode of the prescribed operation,

a source potential is applied to the select line and the control line coupled to the selected memory cell;

a prescribed voltage is applied to the bit line coupled to the first electrode of the selected memory cell and an unselected bit line, adjacent to the bit line coupled to the selected memory cell.