Burst EDO memory device

• US 5,802,010 A
• Filed: 06/10/1996
• Issued: 09/01/1998
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A., Williams, Brett L., Zagar, Paul S.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US08/661,478
• Time in Patent Office: 813 Days
• Field of Search: 365/233.5, 365/238.5, 365/230.06, 365/230.08
• US Class Current: 365/233.5
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.

Claims

1. A memory device having an output enable pin for enabling data to be driven from the memory device and a data output node for driving data from the memory device, comprising:

means for reading data from the memory device in response to an address strobe signal; and

means for placing the data output node in a high impedance state in response to a transition of an output enable signal on the output enable pin, and for maintaining the data output node in a high impedance state despite additional transitions of the output enable signal prior to an additional transition of the address strobe signal.

2. A Memory Module comprising:

a memory device;

a plurality of address signal lines coupled to the memory device to provide an address to the memory device;

an address generation circuit within the memory device, coupled to an address latch signal line, for receiving and advancing the address, to provide multiple data accesses of the memory device in synchronization with multiple transitions of a signal on the address latch signal line after only one address is received; and

at least one data node for transferring data to and from the memory module, wherein data from a first address received from the plurality of address signal lines is driven from the memory module offset in time from when the first address is received, by a predetermined number of transitions of the signal on the address latch signal line.