Data receiving device

• US 5,802,065 A
• Filed: 10/22/1996
• Issued: 09/01/1998
• Est. Priority Date: 10/23/1995
• Status: Expired due to Term

• Current Assignee: Kawasaki Microelectronics Incorporated (Megachips Corporation)
• Original Assignee: Kawasaki Steel Corporation (JFE Holdings Incorporated)
• Inventors: Satoh, Hiroshi, Ogawa, Tetsuo
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): BNIMOUSSA, ABDELHAMID
• Application Number:
  US08/734,777
• Time in Patent Office: 679 Days
• Field of Search: 370/389, 370/392, 370/394, 370/395, 370/396, 370/397, 370/465, 370/466, 370/469, 370/471, 395/200, 375/202, 375/222
• US Class Current: 370/469
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9089 replacing packets in a storage arrangement, e.g. pushout
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/325 in the network layer [OSI layer 3], e.g. X.25 H04L69/16 takes precedence
• CPC Class Codes: H04L 69/326 in the transport layer [OSI layer 4] H04L69/16 takes precedence
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A sequencer 32 is provided with a plurality of protocol processing circuits for independently carrying out at least a part of processes to respective protocol hierarchies of the protocol in response to sequence selection by a sequence selection circuit 28 according to a result of received protocol type identification in a protocol recognition circuit 26. As a result, processes for the respective protocol hierarchies of the protocol or partial processes thereof can be simply and efficiently performed at the same time, and the data receiving device can be configured by the hardware.

Claims

1. A data receiving device for receiving from a network data frame based on any arbitrary protocol in a plurality of protocol hierarchies which are defined from a physical layer to upper layers, comprising:

an input data control circuit for receiving the frame data from the network together with its synchronizing signal and storing them in a register;

a capture register circuit for storing/holding in accordance with information such as a protocol type code, a header length, a frame length, source/destination addresses or source/destination port numbers or socket numbers included in a header for each protocol hierarchy constituting the frame data;

a protocol recognition circuit for identifying a protocol type of each protocol hierarchy from a protocol type code stored in the capture register circuit;

a sequence selection circuit for generating a sequence selection signal used to select a process for each protocol hierarchy of the received frame data in accordance with a result of identification by the protocol recognition circuit and for changing over the sequence selection signal in accordance with a header end signal;

a sequence counter for counting pulse signals of the frame data synchronizing signal;

a sequencer having a function to operate in accordance with a value of the sequence counter and the sequence selection signal, direct to the capture register circuit a timing for storing/holding the information included in the header for each protocol hierarchy and output a second header end timing for directing an end timing for the header when a protocol which is directed by the sequence selection signal and is currently processed has a header having a fixed length; and

a header end timing detection circuit which selects either the first header end timing obtained by comparing a value of the sequence counter with a header length of the currently-received protocol hierarchy or the second header end timing output by the sequencer to generate the header end signal.

2. A data receiving device as set forth in claim 1, wherein the input data control circuit includes a plurality of registers that are connected like a shift register and operate as a pipeline and has a function for inputting the frame data to a first step of the registers using its synchronizing signal and outputting the content of each register to the capture register circuit.

3. A data receiving device as set forth in claim 1, further comprising a frame end detection circuit which counts pulse signals of the frame data synchronizing signal after initialized by a frame counter initialization signal output from the sequencer and generates a signal indicating the end timing for the frame data that is being received by comparing the count value with the frame length.

4. A data receiving device as set forth in claim 3, further comprising an interrupt generation circuit that generates an interrupt signal to an external circuit when the header end signal generated by a header end timing generation circuit or the frame end signal generated by a frame end detection circuit.

5. A data receiving device as set forth in claim 1, wherein the input data control circuit includes a first cut-through circuit for outputting the frame data synchronizing signal to outside in accordance with a direction of a first cut-through signal output from the sequencer and for outputting the content of a specific register within the input data control circuit to outside in synchronism with the frame data synchronizing signal.

6. A data receiving device as set forth in claim 1, wherein the capture register circuit includes a second cut-through circuit for outputting the content of a specific register in the capture register to outside together with a synchronizing signal relative thereto in accordance with a direction of a second cut-through signal output from the sequencer.

7. A data receiving device as set forth in claim 5, further comprising a cut-through selection circuit for selecting either a signal output from the first cut-through circuit or a signal output from the second cutthrough circuit and outputting the selected signal.

8. A data receiving device as set forth in claim 1, wherein the input data control circuit has a configuration to take out a destination address from the header of the protocol hierarchy of the received data and transmit the obtained address to an external circuit.

9. A data receiving device as set forth in claim 1, wherein information stored/held in the capture register circuit can be read out to an external circuit.

10. A data receiving device as set forth in claim 1, wherein a protocol of each protocol hierarchy identified by the protocol recognition circuit can. be read out to an external circuit.

11. A data receiving device as set forth in claim 1, wherein the input data control circuit has a function for verifying a checksum with respect to the received data frame and a function for transmitting a result of verification to an external circuit;

and

wherein the sequencer has a function for directing a timing for starting the checksum operation and a timing for comparing results of the checksum operation to the input data control circuit.