Built-in self test functional system block for UTOPIA interface

• US 5,802,073 A
• Filed: 06/04/1997
• Issued: 09/01/1998
• Est. Priority Date: 09/23/1994
• Status: Expired due to Term

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Platt, Alfred
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/868,853
• Time in Patent Office: 454 Days
• Field of Search: 371/20.1, 371/20.2, 371/20.4, 371/20.5, 371/20.6, 371/22.4, 371/22.5, 371/22.6, 371/67.1, 371/68.1, 371/68.2, 371/22.33, 371/27.1, 371/27.5 , 371/37.02, 371/47.1, 370/241, 370/242, 370/243, 370/244, 370/245, 370/246, 370/248, 370/249, 370/250, 395/183.06, 395/183.15
• US Class Current: 714/733
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04L 2012/5628 Testing

Abstract

An apparatus and method for providing a built-in self-test functional system block (BIST FSB) for self-testing a network interface integrated circuit having a Universal Test & Operations PHYInterface for ATM (UTOPIA) interface. The BIST FSB includes a random number generator, a signature analyzer, two cell counters, and a state machine for controlling the BIST FSB. Means are provided for looping the transmitter of the network interface integrated circuit back to the receiver of the network interface integrated circuit. When the BIST test is started, the state machine waits until the receiver is synchronized. Then user cells are generated and fed to the transmitter for the network interface integrated circuit. At the same time, cells on the receive side are collected and compressed into a signature. When all of the cells have been received, the signature is compared with a precalculated signature. If the signatures match, the test is passed. The BIST FSB in its self-test mode disables user data from entering the network interface integrated circuit and inserts its own data from a random number generator. The BIST monitors data going from the network interface integrated circuit receiver back to BIST. This data is "compressed" into one number and compared with a predetermined signature in a signature analyzer.

Claims

1. A method of self-testing a network interface integrated circuit having a Universal Test &

Operations PHYInterface for ATM (UTOPIA) interface using a built-in self test block, comprising the steps of;

a) generating in a built-in self test block a sequence of user cells with random content, said generated sequence of user cells having a signature;

b) transmitting said sequence of generated user cells from a transmitter contained in said built-in self test block of the network interface integrated circuit and having a state machine contained in the built-in self test block of the network interface integrated circuit wait until the receiving of the transmitted sequence of user cells is synchronized with the transmitted sequence of generated user cells;

c) receiving the transmitted sequence of user cells with a receiver also contained in the built-in self test block of the network interface integrated circuit;

d) compressing the received sequence of user cells into a received sequence signature;

e) comparing in the built-in self test block of the network interface integrated circuit the received sequence signature with the signature of the generated sequence of user cells to determine an error in transmission through the network interface integrated circuit;

f) generating a signal indicating that the network interface integrated circuit has passed a self test if the received sequence signature is the same as the signature of the generated sequence of user cells;

g) controlling the operation of the steps of generating, transmitting receiving, compressing, and comparing with a state machine contained within the built-in self test block of the network interface integrated circuit.

2. A built-in self-test functional system block for self-testing a network interface integrated circuit having a Universal Test &

Operations PHYInterface for ATM (UTOPIA) interface, comprising;

a pseudo-random test signal generator for generating a test signal having a signature, said pseudo-random test signal generator being contained in a built-in self-test functional system block of a network interface integrated circuit;

means for routing the test signal through the network interface integrated circuit to provide a received signal;

means for generating a received-signal signature from the received signal;

a signature analyzer contained in said built-in self-test functional system block of the network interface integrated circuit for comparing the signature of the test signal with the signature of the received signal routed through the network interface integrated circuit;

state machine means contained in said built-in self-test functional system block of the network interface integrated circuit for controlling the operation of the pseudo-random test signal generator, for controlling the means for routing the test signal through the network interface integrated circuit, and for controlling the signature analyzer;

transmitter counter means contained in said built-in self-test functional system block of the network interface integrated circuit for counting the number of cells transmitted from the pseudo-random test signal generator;

receiver counting means contained in the built-in test functional system block of the network interface integrated circuit for counting the number of cells received from the pseudo-random test signal generator;

timeout means contained in the built-in test functional system block of the network interface integrated circuit for providing normal routing of transmit and received signals through the network interface integrated circuit;

multiplexing means contained in said built-in self-test functional system block of the network interface integrated circuit for providing normal routing of transmit and received signal through the network interface integrated circuit and for providing loopback of the test signal through the network interface integrated circuit.