Single chip universal protocol multi-function ATM network interface

• US 5,802,287 A
• Filed: 08/03/1995
• Issued: 09/01/1998
• Est. Priority Date: 10/20/1993
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Bergantino, Paul, Rostoker, Michael D., Stelliga, D. Tony
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US08/510,643
• Time in Patent Office: 1,125 Days
• Field of Search: 370/60, 370/91, 370/230, 370/395, 370/235, 395/200.2, 395/200.13, 395/831, 395/652, 395/830, 395/200.68, 395/200.8
• US Class Current: 370/395.5
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5615 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9021 Plurality of buffers per packet
• CPC Class Codes: H04L 49/9047 including multiple buffers, e.g. buffer pools
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

An asynchronous transfer mode (ATM) processing system interconnection or termination unit is implemented on a single integrated circuit chip. The unit includes a universal protocol device having Virtual Channel Memory (VCR) for storing ATM cells for segmentation and reassembly, a Direct Memory Access (DMA) controller for interconnecting the VCR to a host unit, and a Parallel Cell Interface (PCI) for interconnecting the VCR to an ATM network. A Reduced Instruction Set Computer (RISC) microprocessor controls the DMA controller as well as segmentation and reassembly of Conversion Sublayer Payload Data Unit (CS-PDU)s and transfer between the memory, the host and the ATM network and other operations of the device using single clock cycle instructions. The operating program for the RISC microprocessor is stored in a volatile Instruction Random Access Memory (IRAM) in the form of firmware which is downloaded at initialization. The program can be user designed to accommodate changes in ATM network protocols and congestion handling routines. A Pacing Rate Unit (PRU) includes a global pacing rate register which automatically reduces the maximum transmission rate of ATM cells in response to a sensed congestion condition in the ATM network.

Claims

1. An information processing system interconnection device for facilitating high speed transmission of divergent types of data between an electronic data network and a host unit, the data network transferring data in the form of cells, comprising:

a substrate;

a network interface formed on said substrate for facilitating the transferring of cells in a data network protocol to and from the data network;

a host interface formed on said substrate for facilitating the transferring of cells in a host protocol to and from the host unit; and

a universal protocol device formed on said substrate for coupling said network interface and said host interface together to facilitate the high speed and reliable transmission of divergent types of data therebetween;

said universal protocol device being integrated with;

an adaptive error detection and correction apparatus for an asynchronous transfer mode (ATM) network device;

a random number generating apparatus for an interface unit of a carrier sense with multiple access and collision detect (CSMA/CD) Ethernet data network;

a router for a multiplex communication network; and

a hub for an electronic communication network.

2. A device according to claim 1, wherein said adaptive error detection and correction apparatus for said ATM network device includes:

a sensing unit for detecting a congestion condition in an ATM network;

a global pacing rate unit responsive to a detected congestion for adaptively reducing a maximum allowable transmission ratio of ATM cells containing information to idle ATM cells, said global unit in including a global pacing rate register for storing said maximum allowable transmission ratio;

a processor coupled to said global pacing rate unit for storing in said global pacing rate register a number corresponding to a relatively high maximum allowable transmission ratio in the absence of a sensed congestion condition and for storing in said global pacing state register another number corresponding to a relatively low maximum allowable transmission ratio in response to a sensed congestion condition;

a controller coupled to said global pacing rate unit for adjusting the maximum allowable transmission in accordance with the number stored in said global pacing rate register; and

a plurality of peak pacing rate counters reset to predetermined value upon decrementation to zero, wherein the predetermined values correspond to service intervals for segmentation of conversion sublayer payload data units (CS-PDU).

3. A device according to claim 1, wherein said router for a multiplex communication network includes:

a packet memory for storing data packets;

a reduced instruction set computer (RISC) processor for converting the packets between a local area network (LAN) protocol and a wide area network (WAN) protocol;

a LAN interface;

a WAN interface;

a direct memory access (DMA) controller for transferring packets between said packet memory and said LAN interface and said WAN interface;

a packet attribute memory unit for storing attributes of the data packet;

an attribute processor for performing non-linear hashing algorithms on an address of a packet being processed for accessing a corresponding attribute of said packet in the packet memory unit; and

an address window filter for identifying the address of a packet being processed by examining only a predetermined portion of said address.

4. A device according to claim 3, wherein the RISC processor includes:

a computing unit; and

a programmable instruction memory connected to the computing unit for storing a program for controlling the computing unit; and

wherein the instruction memory includes a volatile storage unit and means for downloading said program into the storage unit in the form of firmware.

5. A device as according to claim 1, wherein said universal protocol device further includes a volatile memory for storing the cells;

and

wherein the host interface is a Direct Memory Access (DMA) controller for transferring said cells in said host protocol between the volatile memory, the processor and said host unit.

6. A device according to claim 5, wherein the processor controls the DMA controller.

7. A d device according to claim 5, further comprising an auxiliary port for interconnecting the volatile memory and said host unit independently of the host interface.

8. A device as in claim 2, in which the processor comprises a Reduced Instruction Set Computer (RISC) microprocessor.

9. A device according to claim 2, wherein said processor further includes:

means for assigning the plurality of counters to selected CD-PDU units.

10. A device according to claim 9, wherein said processor further includes:

sensing means for determining whether the segmentation of the selected CD-PDU units is determining whether the segmentation of the selected CD-PDU is within a respective service interval.

11. A device according to claim 1, wherein said random number generating apparatus for an interface unit of a carrier sense with multiple access and collision detect (CSMA/CD) Ethernet data network, includes:

a transmit backoff unit responsive to a network collision signal and a random number for implementing a backoff algorithm;

a dual mode random number generator having a multiplex for switching the random number generator between modes in accordance with the serial address bits of a data packet being processed by the interface unit.

12. A device according to claim 11, wherein said dual mode random number generator includes a 25 stage linear feedback shift register.

13. A device according to claim 12, wherein said multiplex includes:

a pair of signal input connect to the outputs of the 18th and 22nd stages of said shift register.

14. A device according to claim 13, wherein said random number generator apparatus further includes:

a switch input connected to receive the serial address bits and an output connected in circuit to an input of the shift register.

15. A device according to claim 3, wherein said address window filter is a dynamic window filter.

16. A device according to claim 3, wherein an address window filter is a static window filter.

17. A device according to claim 1, wherein said hub for an electronic communication network includes:

a packet memory for storing data packets;

a reduced instruction set computer (RISC) processor for processing the packets;

a plurality of modems access interface units; and

a direct memory access controller for transferring packet between the packet memory and the interfaces.

18. A device according to claim 17, further comprising:

an attribute processor; and

a window filter which corresponds to a router window filter.

19. An Asynchronous Transfer Mode (ATM) network termination device, comprising:

a single chip having mounted thereon;

an asynchronous transfer mode (ATM) network;

a universal protocol device comprising a virtual channel memory for storing ATM cells, and a processor connected to the virtual channel memory for segmenting and reassembling said ATM cells stored in the virtual channel memory;

a network interface connected to the virtual channel memory, the processor and an ATM network for transferring ATM cells including segmented Conversion Sublayer Payload Data Units (CS-PDUs) between the memory, the processor and the ATM network, each CS-PDU including actual data to be transmitted, a header and a trailer; and

a host interface connected to the virtual channel memory, the processor and the host unit for transferring unsegmented CS-PDUs between the virtual channel memory, the processor and a host unit;

wherein said universal protocol device is integrated with;

an adaptive error detection and correction apparatus for an asynchronous transfer mode (ATM) network device;

a random number generating apparatus for an interface unit of a carrier sense with multiple access and collision detect (CSMA/CD) Ethernet data network;

a router for a multiplex communication network; and

a hub for an electronic communication network.

20. A device as in claim 19, in which the processor comprises a Reduced Instruction Set Computer (RISC) microprocessor.

21. A device as in claim 19, in which the processor controls the virtual channel memory, the network interface and the host interface using instructions generated in a single clock cycle.

22. A device as in claim 19, in which the instruction memory comprises a volatile storage unit and means for downloading said program into the storage unit in the form of firmware.

23. A device according to claim 19, wherein the host interface is a Direct Memory Access (DMA) controller for facilitating the transfer of unsegmented CS-PDUs between the virtual channel memory and said host unit.

24. A device according to claim 23, wherein the processor controls the DMA controller operations.

25. A device as in claim 19, further comprising an auxiliary port for interconnecting the virtual channel memory and said host unit independently of the host interface.

26. A device according to claim 19, wherein the auxiliary port comprises a parallel interface.

27. A device according to claim 19, further comprising:

a rate pacing unit for automatically reducing a maximum allowable transmission ratio of ATM cells containing information ATM cells that are idle in response to a sensed congestion condition in said ATM network.

28. An asynchronous transfer mode (ATM) termination device, comprising:

a substrate;

a single chip ATM processing interconnection unit including a universal protocol device disposed on said substrate for controlling ATM line operations in response to a plurality of ATM adaption layers including data streams of cells;

said universal protocol device including;

random access volatile memory means for storing and retrieving individual ones of the cells in said data stream of cells to help facilitate the segmentation and reassembly of said data stream cells to effect high speed transmission of divergent types of data over an ATM network;

direct memory access controller means for coupling said memory means to said ATM network;

processor means coupled to said memory means and said direct memory access controller means for initiating controller means operations to help facilitate the ATM line operations and effect asynchronous data transfers between said ATM network and a host unit through said memory means; and

operating program means coupled to said processor means for controlling said processor means to accommodate different types of ATM network protocols;

said operating program means enabling said processor means and said controller means to cooperate to effect at least the segmentation and reassembly of said plurality of ATM adaption layers for high speed transmission of divergent types of data over said ATM network

wherein said universal protocol device is integrated with;

an adaptive error detection and correction apparatus for an asynchronous transfer mode (ATM) network device;

a random number generating apparatus for an interface unit of a carrier sense with multiple access and collision detect (CSMA/CD) Ethernet data network;

a router for a multiplex communication network; and

a hub for an electronic communication network.

29. An Asynchronous Transfer Mode (ATM) network termination device, according to claim 28, wherein said random access volatile memory means is a virtual channel memory for storing ATM cells;

and

wherein said processor means is a processor connected to the virtual channel memory for segmenting and reassembling said ATM cells stored in the virtual channel memory, said processor including;

a computing unit; and

wherein said operating program means includes;

a programmable instruction memory connected to the computing unit for storing a program for controlling the computing unit.

30. A device according to 29, wherein the instruction memory comprises a volatile storage unit and means for downloading said program into the storage unit in the form of firmware.

31. A device as in claim 29, in which the computing unit comprises a Reduced Instruction Set Computer (RISC) microprocessor.

32. A device according to claim 29, further comprising:

a network interface for transferring ATM cells including segmented Conversion Sublayer Payload Data Unit (CS-PDU)s between the virtual channel memory and an ATM network; and

a host interface for transferring unsegmented CD-PDUs between the virtual channel memory and the host unit.

33. A device according to claim 32, wherein the host interface and the direct memory access controller cooperate to facilitate transferring unsegmented CS-PDUs between the virtual channel memory and said host unit.

34. A device as in claim 33, in which the processor initiates direct memory access controller operations.

35. A device as in claim 29, further comprising an auxiliary port for interconnecting the memory and said host unit independently of the host interface.

36. A device as in claim 35, in which the auxiliary port comprises a parallel interface.

37. A device as in claim 29, further comprising a global rate pacing unit for automatically reducing a maximum allowable transmission ratio of ATM cells containing information to idle ATM cells in response to a sensed congestion condition in said ATM network.

38. An information processing system interconnection device for facilitating high speed transmission of divergent types of data between an electronic data network and a host unit, the data network transferring data in the form of cells, comprising:

a substrate;

a network interface formed on said substrate for facilitating the transferring of cells in a data network protocol to and from the data network;

a host interface formed on said substrate for facilitating the transferring of cells in a host protocol to and from the host unit; and

a universal protocol device formed on said substrate for coupling said network interface and said host interface together to facilitate the high speed transmission of divergent types of data therebetween,

wherein said universal protocol device is integrated with;

an adaptive error detection and correction apparatus for an asynchronous transfer mode (ATM) network device;

a random number generating apparatus for an interface unit of a carrier sense with multiple access and collision detect (CSMA/CD) Ethernet data network;

a router for a multiplex communication network; and

a hub for an electronic communication network.

39. A device according to claim 38, wherein said universal protocol device includes:

a sensing unit for detecting a congestion condition in an ATM network;

a global pacing rate unit responsive to a detected congestion for adaptively reducing a maximum allowable transmission ratio of ATM cells containing information to idle ATM cells, said global unit including;

a global pacing rate register for storing said maximum allowable transmission ratio;

a processor coupled to said global pacing rate unit for storing in said global pacing rate register, a number corresponding to a relatively high maximum allowable transmission ratio in the absence of a sensed congestion condition and for storing in said global pacing state register another corresponding to a relatively low maximum allowable transmission ratio in response to a sensed congestion condition;

a controller coupled to said global pacing rate unit adjusts the maximum allowable transmission in accordance with the number stored in said global pacing rate register; and

a plurality of peak pacing rate counters reset to predetermined value upon decrementation to zero, wherein the predetermined values correspond to service intervals for segmentation of conversion sublayer payload data units (CS-PDU).

40. A device according to claim 39, wherein said random number generating apparatus, includes:

a transmit backoff unit responsive to a network collision signal and a random number for implementing a backoff algorithm;

a dual mode random number generator having a multiplex for switching the random number generator between modes in accordance with the serial address bits of a data packet being processed by the interface unit.

41. A device according to claim 39, wherein said universal protocol device includes:

a packet memory for storing data packets;

a reduced instruction set computer (RISC) processor for converting the packets between a local area network (LAN) protocol and a wide are network (WAN) protocol;

a LAN interface;

a WAN interface;

a direct memory access (DMA) controller transfers packets between said packet memory and said LAN interface and said WAN interface;

a packet attribute memory unit for storing attributes of the data packet; and

an attribute processor performs non-linear hushing algorithms on an address of a packet being processed for accessing a corresponding attribute of said packet in the packet memory unit;

an address window filter identifies the address of a packet being processed by examining only a predetermined portion of said address.

42. A device according to claim 39, wherein said universal protocol device includes:

a packet memory for storing data packets;

a reduced instruction set computer (RISC) processor for processing the packets;

a plurality of modems access interface units; and

a direct memory access controller for transferring packet between the packet memory and the interfaces.

43. A device according to claim 39, wherein said universal protocol device includes:

a volatile memory for storing and retrieving individual ones of the cells to help facilitate the segmentation and reassembly of the cells to effect high speed transmission of divergent types of data over the electronic data network;

a direct memory access controller for coupling said volatile memory to the electronic data network to facilitate the segmentation and reassembly of the cells;

a processor connected to the volatile memory and said direct memory access controller for converting said cells between a data network protocol and a host protocol;

a network interface connected to the volatile memory, the processor, the direct memory access controller, and the data network for facilitating the transferring of cells in said data network protocol between the volatile memory, the processor, the direct memory access controller, and said data network; and

a host interface connected to the volatile memory, the processor, the direct memory access controller, and the host unit for facilitating the transferring of cells in said host protocol between the volatile memory, the processor, the direct memory access controller and said host unit;

in which the processor comprises;

a computing unit; and

a programmable instruction memory connected to the computing unit for storing a program for controlling the computing unit;

said program enabling said processor and said direct memory access controller to cooperate to effect at least the segmentation and reassembly of the cells from said host protocol to said date network protocol and from said data network protocol to said host protocol.