Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed
First Claim
1. A virtual network comprising:
- plural distributed virtual computers interconnected over a communication network of individual links;
each distributed virtual computer comprising at least two respective ports each being connected over a respective link to another respective distributed virtual computer in the network;
each distributed virtual computer being connected to or resident within its own host computer;
each distributed virtual computer comprising reconfigurable FPGA logic elements, at least one of the FPGA elements being configured to have control capability over at least some of the remaining FPGA elements to react to instructions received from a host or from other nodes on the network to re-configure FPGA elements in the computation array to carry out a required task; and
wherein at least the one or FPGA element is configured to have compiling capability to generate configuration bit files from received instructions defining how said at least some of said remaining FPGA elements are to be reconfigured so as to enable them to carry out said received instructions.
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0 Petitions
Accused Products
Abstract
A virtual network consists of many distributed virtual computers interconnected over a communication network of individual links, such as optical fibers or electrical conductors, for example. Each distributed virtual computer has at least two ports connected over respective links to other respective distributed virtual computers on the network. Each distributed virtual computer is connected to or resident within its own host, each host typically being a conventional computer such as a personal computer or a work station, for example, although at least one of the hosts may itself be another virtual computer. Each distributed virtual computer has reconfigurable logic elements such as an FPGA or an array of FPGAs.
332 Citations
28 Claims
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1. A virtual network comprising:
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plural distributed virtual computers interconnected over a communication network of individual links; each distributed virtual computer comprising at least two respective ports each being connected over a respective link to another respective distributed virtual computer in the network; each distributed virtual computer being connected to or resident within its own host computer; each distributed virtual computer comprising reconfigurable FPGA logic elements, at least one of the FPGA elements being configured to have control capability over at least some of the remaining FPGA elements to react to instructions received from a host or from other nodes on the network to re-configure FPGA elements in the computation array to carry out a required task; and wherein at least the one or FPGA element is configured to have compiling capability to generate configuration bit files from received instructions defining how said at least some of said remaining FPGA elements are to be reconfigured so as to enable them to carry out said received instructions. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A virtual network comprising:
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plural distributed virtual computers, each of said plural distributed virtual computers being adapted for connection with a respective host; plural communication links connecting each of said plural distributed virtual computers with at least two others of said plural distributed virtual computers; each distributed virtual computer comprising; (A) at least two respective ports each being connected to a respective one of said links; (B) plural reconfigurable FPGA logic elements comprising; (1) a control set of reconfigurable FPGA elements being configured to have control capability for compiling a request received from a host or from other nodes on the network to generate configuration bit files defining a logic configuration for carrying out a process corresponding to said request; (2) a computation set of reconfigurable FPGA elements adapted to be reconfigured by said control set of FPGA elements in accordance with said configuration bit files so as to be capable of carrying out a corresponding process on operand data; and wherein at least the control set of FPGA elements are configured to have compiling capability to generate configuration bit files from received instructions defining how said computation set of FPGA elements are to be reconfigured so as to enable them to carry out processes corresponding to said received instructions. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A method of operating as a computer a reconfigurable node in a computer network of plural reconfigurable nodes interconnected by plural communication links, said reconfigurable node comprising reconfigurable logic array elements which are reconfigurable in accordance with a configuration bit file so as to become adapted to perform an operation in accordance with a predetermined reconfiguration algorithm which generates said configuration bit file from a definition of said operation, said method comprising:
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storing an executable code defining a sequence of operations to be executed in sequence; executing said executable code operation-by-operation in order of said sequence, said executing comprising; at the time of the execution of at least one of said operations, computing exclusively from the portion of said executable code defining said one operation a corresponding configuration bit file representative of said one operation in accordance with said reconfiguration algorithm, and reconfiguring said reconfigurable node in accordance with said corresponding configuration bit file. - View Dependent Claims (15, 16, 17)
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18. A method of operating a reconfigurable logic array which is reconfigurable in response to different configuration bit files defining different logic configurations adapted to perform different operations, said configuration bit files susceptible of being produced by a reconfiguration algorithm based upon definitions of said different operations, said method comprising:
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storing an executable code defining a sequence of operations to be executed in sequence; executing said executable code operation-by-operation in order of said sequence, said executing comprising; at the time in said sequence for execution of at least one of said operations, computing exclusively from the portion of said executable code defining said one operation a corresponding configuration bit file representative of said one operation in accordance with said reconfiguration algorithm, and reconfiguring said reconfigurable logic array in accordance with said corresponding configuration bit file in time for said reconfigurable logic array to carry out said one operation in the order of said sequence. - View Dependent Claims (19, 20, 21, 22)
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23. A method of operating a reconfigurable logic array reconfigurable in response to respective configuration bit files defining respective logic configurations into which said reconfigurable logic array can be configured, at least one of said respective logic configurations at a time, to perform respective operations, said respective configuration bit files susceptible of being produced by a reconfiguration algorithm based upon definitions of said respective operations, said method comprising:
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storing an executable code comprising images of operations in a sequence of operations to be executed; executing said executable code operation-by-operation in order of said sequence, said executing comprising; at the time in said sequence for execution of at least one of said operations, computing exclusively from said image of the one operation a corresponding configuration bit file representative of said one operation in accordance with said reconfiguration algorithm, and reconfiguring said reconfigurable logic array in accordance with said corresponding configuration bit file in time for said reconfigurable logic array to carry out said one operation in the order of said sequence. - View Dependent Claims (24, 25, 26, 27, 28)
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Specification