Data interface

• US 5,802,351 A
• Filed: 02/05/1996
• Issued: 09/01/1998
• Est. Priority Date: 02/14/1995
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Original Assignee: Nokia Mobile Phones UK Limited (Nokia Corporation)
• Inventors: Frampton, Simon
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US08/596,720
• Time in Patent Office: 939 Days
• Field of Search: 395/500, 395/477, 395/800, 395/200.16, 395/384, 395/387, 364/131, 370/62, 370/259, 379/58, 379/59
• US Class Current: 703/27
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: H04M 1/724 User interfaces specially adapted for cordless or mobile telephones

Abstract

A data buffer (23) is positionable between processing devices, such as microcontroller (21) and a digital signal processor (22). Messages are transmitted between the devices via a dual port RAM buffer (31). The amount of storage allocated for transfers in each direction is adjustable via a size register (42) so that, at any particular time, the optimum amount of storage is provided for a transfer in a particular direction. The buffer is particular suited to applications in mobile telephones.

Claims

1. A data buffer positionable between a first processing means and a second processing means, comprising:

storage means arranged to buffer data signals generated by each of said processing means for reception by the other of said processing means, and

programmable storage allocation means arranged to adjust an amount of storage provided by said storage means for buffering data signals generated by each of said processing means;

wherein said programmable storage allocation means is comprised of address generating means for generating addressing signals for the writing of data to said storage means or the reading of data from said storage means; and

wherein said address signal generating means is arranged to generate addressing signals initiated from a predetermined value, said address signal generating means further including decoding means for selectively applying an offset to said addressing signals, depending upon whether a writing operation or a reading operation is being performed.

2. A data buffer according to claim 1, wherein said storage means is comprised of a two-port random access memory, having one port for data transfer with said first processing means and a second port for data transfer with said second processing means.

3. A data buffer according to claim 1, wherein said programmable storage allocation means is further comprised of address interpretation means, arranged to enable said address generating means in response to a particular addressing signal generated by said first processing means or by said second processing means.

4. A data buffer according to claim 1, wherein said address generating means is arranged to generate addressing signals initiated from a predetermined value and to increment said addressing signals so as to address a plurality of locations in said storage means.

5. A data buffer according to claim 1, wherein said storage allocation means includes a register defining a location in said storage means that marks a boundary between first storage locations allocated for buffering data signals generated by said first processing means and second storage locations allocated for buffering data signals generated by said second processing means.

6. A data buffer according to claim 1, wherein said first processing means is comprised of a microcontroller and said second processing means is comprised of a digital signal processor, and wherein said data buffer is positioned between said microcontroller and said digital signal processor.

7. A data buffer according to claim 6, wherein said microcontroller is interfaced to a keypad and a display of a mobile telephone and the digital signal processor is interfaced to a microphone and a loudspeaker of said mobile telephone.

8. A method of buffering data being transferred between a first processing means and a second processing means, comprising steps of:

storing data generated by either of said processing means in a storage device;

reading said stored data by the other of said processing means;

and programmably adjusting an amount of storage provided by said storage device for buffering data signals generated by each of said processing means;

wherein the step of programmably adjusting includes a step of generating addressing signals for the writing of data to the storage device or the reading of data from the storage device;

wherein the step of generating addressing signals generates addressing signals initiated from a predetermined value, and further comprising a step of

selectively applying an offset to the addressing signals, depending upon whether a writing operation or a reading operation is being performed.

9. A mobile telephone having a first data processor and a second data processor each programmed for performing certain tasks during the operation of said mobile telephone, said mobile telephone comprising:

a two port storage device comprised of X storage locations, said two port storage device having a first input/output port coupled to a data path of said first data processor and a second input/output port coupled to a data path of said second data processor, said two port storage device having, at any given time, Y storage locations allocated to said first data processor for storing data within and Z storage locations allocated to said second data processor for storing data within, where X is at least equal to Y+Z; and

a programmable control circuit coupled to said storage device, said programmable control circuit having a programming input coupled to at least one of said data processors, said control circuit being responsive to programming information received through said programming input for setting the values of Y and Z;

wherein said first data processor is comprised of a microcontroller and said second data processor is comprised of a digital signal processor; and

wherein

wherein during an initialization procedure of said mobile telephone said microcontroller transmits at least a portion of an operating program to said digital signal processor through said two port storage device, and wherein during said initialization procedure said programmable control circuit is programmed such that Y>

Z.

10. A mobile telephone according to claim 9, wherein said microcontroller is interfaced at least to a user interface portion of said mobile telephone and said digital signal processor is interfaced at least to a voice handling portion of said mobile telephone.