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Array processing system with each processor including router and which selectively delays input/output of individual processors in response delay instructions

  • US 5,802,385 A
  • Filed: 08/16/1995
  • Issued: 09/01/1998
  • Est. Priority Date: 09/21/1994
  • Status: Expired due to Term
First Claim
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1. Parallel processing apparatus comprising:

  • an array of data processors arranged to operate synchronously;

    a plurality of data buses; and

    each data processor having first and second I/O means for transferring data between a respective processor and a respective pair of data buses, a plurality of data processors being connected to each of the data buses and each data processor being connected, via said first and second I/O means, to a different pair of data buses, wherein each processor includes selectively operable routing means for inputting said data from a first processor via one of said respective pair of buses to said first I/O means and selectively routing said data directly from said first I/O means through said second I/O means to a second processor via the other of said respective pair of buses.

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