Array processing system with each processor including router and which selectively delays input/output of individual processors in response delay instructions
First Claim
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1. Parallel processing apparatus comprising:
- an array of data processors arranged to operate synchronously;
a plurality of data buses; and
each data processor having first and second I/O means for transferring data between a respective processor and a respective pair of data buses, a plurality of data processors being connected to each of the data buses and each data processor being connected, via said first and second I/O means, to a different pair of data buses, wherein each processor includes selectively operable routing means for inputting said data from a first processor via one of said respective pair of buses to said first I/O means and selectively routing said data directly from said first I/O means through said second I/O means to a second processor via the other of said respective pair of buses.
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Abstract
In one aspect, the invention provides parallel processing apparatus comprising an array of data processors 4. arranged to operate synchronously, and a plurality of data buses. Each data processor 4 has first and second I/O means 16H, 16V for transfer of data between the processor 4 and respective data buses H,V a plurality of processors 4 being connected to each of the data buses H,V and each processor 4 being connected, via said I/O means 16H, 16V, to a different pair of data buses H,V. Each processor 4 includes selectively operable routing means 32H, 32V for interconnecting the first and second I/O means 16H, 16V to transfer data between the buses H,V connected thereto.
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Citations
31 Claims
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1. Parallel processing apparatus comprising:
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an array of data processors arranged to operate synchronously; a plurality of data buses; and each data processor having first and second I/O means for transferring data between a respective processor and a respective pair of data buses, a plurality of data processors being connected to each of the data buses and each data processor being connected, via said first and second I/O means, to a different pair of data buses, wherein each processor includes selectively operable routing means for inputting said data from a first processor via one of said respective pair of buses to said first I/O means and selectively routing said data directly from said first I/O means through said second I/O means to a second processor via the other of said respective pair of buses. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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- 12. Parallel processing apparatus comprising an array of data processors arranged to operate synchronously in accordance with a clock signal, each processor having data I/O means connecting the respective processor to at least one data bus to which a plurality of the processors are connected, and each processor having a program memory and being arranged to perform a sequence of operations in accordance with a sequence of instructions stored in said program memory of the processor, wherein each processor includes selectively operable output delay means for delaying data supplied to the I/O means in response to an instruction from said program memory to delay said output, following an instruction to output that data to the bus, until a cycle of the clock signal when the bus is free.
- 24. Parallel processing apparatus comprising an array of data processors arranged to operate synchronously in accordance with a clock signal, each processor having data I/O means connection a respective processor to at least one data bus to which a plurality of said processors are connected, and each processor having a program memory and being arranged for performing a sequence of operations in accordance with a sequence of instructions stored in said program memory of the respective processor, wherein each processor includes selectively operable input delay means for delaying data supplied by the bus to the I/O means in response to an instruction from said program memory to delay said input until input of that data can be effected by an instruction.
Specification