Method and system for reducing memory access latency by providing fine grain direct access to flash memory concurrent with a block transfer therefrom

• US 5,802,554 A
• Filed: 03/05/1997
• Issued: 09/01/1998
• Est. Priority Date: 02/28/1995
• Status: Expired due to Term

• Current Assignee: Panasonic Corporation Of North America (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Technologies, Inc. (Panasonic Holdings Corporation)
• Inventors: Caceres, Ramon, Bershad, Brian, Douglis, Frederick, Marsh, Brian D.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Thai, Tuan V.
• Application Number:
  US08/813,011
• Time in Patent Office: 545 Days
• Field of Search: 364/DIG. 1, 364/243.4, 365/49, 365/185.33, 711/5, 711/103, 711/118, 711/119, 711/205
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 2212/2022 Flash memory

Abstract

A system and method for reducing access latency to stable storage are described. A technique referred to as fault trickling is used to improve access latency to stable storage such as flash memory. In particular, data requests from a central processing unit are preferentially satisfied by a memory management unit providing access to a main memory. When the requested data does not reside in the main memory, however, the memory management unit satisfies the request by providing direct fine-grain access to the flash memory. In addition, concurrently with satisfying the data request directly from the flash memory, a block transfer is initiated from the flash memory to the main memory. Once the block transfer is completed, a memory map, such as an address translation table, is updated to indicate that the data now resides in the more convenient source of data--the main memory. Accordingly, subsequent data requests, for that or proximately located data, can be satisfied by accessing the main memory.

Claims

1. A data processing system including:

a flash memory device for storing data;

a main memory device, separate from the flash memory device, and having a relatively faster access time than the flash memory device, for storing data;

processor means for generating requests for data;

a memory management unit which, responsive to the requests received from the processor means, provides direct single word access by the processor means to data stored in the flash memory device when a data request by the processor means is for data not presently stored in the main memory device, said memory management unit including;

means for concurrently transferring blocks of data, including the data requested by the processor, from the flash memory device to the main memory device when a data request by the processor means is for data not presently stored in the main memory device, and

means for comparing each request for data received from the processor to the data that has been transferred to the main memory device to preferentially provide the requested data from the main memory device.

2. The data processing system of claim 1, wherein the memory management unit is also for concurrently transferring blocks of data, including the data requested by the processor, from the flash memory device to the main memory device when a data request by the processor means is for data not presently stored in the main memory device.

3. The data processing system of claim 1, wherein the memory management unit includes

an address translation means which, for at least first accesses of stored data, maps a virtual address used by the processor to request data directly to a physical address of the flash memory device.

4. The data processing system of claim 1, wherein the memory management unit includes an address translation table which, for at least first accesses, maps a virtual address used by the processor to request data directly to a physical address of the flash memory device and, after first accesses, maps the virtual address to a physical address of the main memory.

5. A method for accessing data in data processing system including a central processing unit (CPU), a flash memory device and a main memory device comprising the steps of:

requesting data by the CPU;

determining that the requested data is not stored in the main memory;

providing the CPU with direct single word access to the data from the flash memory device;

providing the accessed data to the CPU;

memory mapping virtual addresses of data not stored in the main memory device to physical address of the flash memory device;

concurrently with the direct single word access, commencing a block transfer of data, including the requested data, from the flash memory device to the main memory device; and

modifying, upon completion of the block transfer, the memory map such that the virtual addresses of data transferred to the main memory now correspond to physical addresses in the main memory rather than physical addresses in the flash memory.

6. The method of claim 5, further comprising the step of concurrently with the directly accessing step,

commencing a block transfer of data, including the requested data, from the flash memory device to the main memory device.

7. The method of claim 5, further comprising the step of

memory mapping virtual addresses of data not stored in the main memory device to physical address of the flash memory device.

8. The method of claim 5, further comprising the step of

comparing the virtual address to an address translation table;

and

determining whether to access the requested data from the main memory device or to access the requested data directly from the flash memory device.

9. A data processing system including:

processor means for generating requests for data;

a flash memory device for storing data;

a main memory device, separate from the flash memory device, and having a relatively faster access time than the flash memory device, for storing data;

a cache memory device, separate from the flash memory device and the main memory device, and having a relatively faster access time than either the main memory device or the flash memory device, for storing data;

a memory management unit which, responsive to the requests received from the processor means, provides direct single word access by the processor means to data stored in the flash memory device when a data request by the processor means is for data not presently stored in the main memory device, said memory management unit including an address translation means which, for at least first accesses of stored data, maps a virtual address used by the processor to request data directly to a physical address of the flash memory device, said memory management unit including;

means for concurrently transferring blocks of data, including the data requested by the processor, from the flash memory device to the main memory device when a data request by the processor means is for data not presently stored in the main memory device, and

means for comparing each request for data received from the processor to the data that has been transferred to the main memory device to preferentially provide the requested data from the main memory device.

10. A method for accessing data in data processing system including a central processing unit (CPU), a cache memory device, a main memory device separate from the cache memory device and a flash memory device separate from both the cache and main memory devices, the method comprising the steps of:

requesting data by the CPU;

providing the CPU with direct single word access to the data in the flash memory device by mapping virtual addresses of data not stored in the main memory device to physical addresses of the flash memory device by way of a memory management unit;

concurrently with the direct single word access, commencing a block transfer of data, including the requested data, from the flash memory device to the main memory device; and

modifying, upon completion of the block transfer, the memory map such that the virtual addresses of data transferred to the main memory now correspond to physical addresses in the main memory rather than physical addresses in the flash memory.