Computer system including a refresh controller circuit having a row address strobe multiplexer and associated method

• US 5,802,555 A
• Filed: 03/13/1997
• Issued: 09/01/1998
• Est. Priority Date: 03/15/1995
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Shigeeda, Akio
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/816,460
• Time in Patent Office: 537 Days
• Field of Search: 711/105, 711/106, 711/211, 711/167, 365/222, 365/230.02, 365/233, 365/193
• US Class Current: 711/106
• CPC Class Codes: G06F 1/1616 with folding flat displays, e.g. laptop computers or notebooks having a clamshell configuration, with body parts pivoting to an open position around an axis parallel to the plane they define in closed position
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A refresh controller circuit in an electronic device, such as a microprocessor unit of a portable computer adapted for docking into a docking station, and a method of operating a computer system to control a refresh operation, are disclosed. The refresh controller circuit includes a refresh clock circuit, a refresh queue counter circuit, and an idle condition detector responsive to the absence of memory read and write requests over a period of time. The refresh controller circuit also includes a latch for storing bits indicative of a self refresh mode enable and a refresh queuing enable. A suspend enable circuit is fed by an output of the idle condition detector and a stop request line, and a refresh request circuit is responsive to outputs of the refresh queue counter, the idle condition detector, and the refresh queuing enable. A refresh row address strobe (RAS) circuit has inputs from the self-refresh circuit and the suspend enable circuit. A RAS multiplexer has inputs for an output of the refresh RAS circuit and for data access RAS, and has an output connected to RAS output terminals of the memory controller for connection to an external dynamic random access memory to effect refresh. The microprocessor unit, which may be integrated onto a single integrated circuit chip with the refresh and memory controller, has a first level write-through cache in combination with a significantly smaller second level write-back cache. The disclosed microprocessor unit also includes configuration registers and circuitry for controlling the access thereto, including circuitry for determining memory address type and bank sizes.

Claims

1. A refresh controller circuit in a single chip memory controller responsive to a stop request from a microprocessor and also having row address strobe (RAS) output terminals for connection to an external memory, the refresh controller circuit comprising:

an idle condition detector for detecting an idle condition responsive to absence of memory read or write requests for a period of time;

a refresh queue counter circuit;

a refresh clock circuit;

a control latch for storing at least one bit indicative of a self refresh mode enable and at least one other bit indicative of a refresh queuing enable;

a self refresh circuit which is enabled by said self refresh mode enable and has an input coupled to said refresh clock circuit;

a suspend enable circuit coupled to an output of said idle condition detector and to a stop request line;

a refresh row address strobe circuit having an output, and a first input coupled to an output of said self refresh circuit and a second input coupled to an output of said suspend enable circuit; and

a row address strobe multiplexer having an output coupled to said RAS output terminals and a first input for data access RAS and a second input coupled to the output of said refresh row address strobe circuit.

2. The refresh controller circuit of claim 1, wherein the refresh queue counter circuit has a clock input coupled to receive a refresh clock signal from the refresh clock circuit, said refresh queue counter circuit for generating a refresh request signal responsive to receiving a selected number of pulses of the refresh clock signal.

3. The refresh controller circuit of claim 2, further comprising:

a row address strobe generator circuit, having an output coupled to the first input of the row address strobe multiplexer, for generating row address strobe signals to the external memory;

a column address strobe generator circuit for generating column address strobe signals to the external memory;

control logic, coupled to the refresh queue counter circuit, for controlling the row address strobe and column address strobe generator circuits to generate row address strobe and column address strobe signals, respectively, to effect a refresh operation responsive to the refresh request signal from the refresh queue counter circuit.

4. The refresh controller circuit of claim 3, wherein the suspend enable circuit generates a suspend signal responsive to said idle condition detector detecting an idle condition in combination with a stop request signal on the stop request line;

and wherein the control logic is also coupled to the suspend enable circuit, said control logic for controlling the row address strobe generator circuit to generate at least one row address strobe signal from the suspend refresh row address strobe circuit to effect refresh operations responsive to the suspend signal.

5. The refresh controller circuit of claim 3, wherein the row address strobe generator circuit has a plurality of row address strobe outputs, for controlling refresh and access in a multiple-bank memory.

6. The refresh controller circuit of claim 5, wherein the refresh row address strobe circuit generates a plurality of row address strobe signals, corresponding to the plurality of row address strobe outputs of the row address strobe generator circuit.

7. A refresh controller circuit comprising:

an idle condition detector for detecting an idle condition responsive to absence of memory read or write requests for a period of time;

a refresh clock circuit for generating a refresh clock signal;

a self refresh circuit having an input receiving the refresh clock signal, having an input for receiving a self refresh mode signal, and having an output for presenting the refresh clock signal responsive to the self refresh mode signal indicating that self refresh mode is not enabled, and for presenting a row address strobe disable state responsive to the self refresh mode signal indicating that self refresh mode is enabled;

a suspend enable circuit, having an input coupled to the idle condition detector and having an input for receiving a stop request signal, for generating a suspend signal responsive to receiving the stop request signal during an idle condition;

a suspend refresh row address strobe circuit having a first input coupled to the output of the self refresh circuit and having a second input coupled to receive the suspend signal, for generating at least one row address strobe signal corresponding to the output of the self refresh circuit responsive to receiving the suspend signal; and

a row address strobe generator circuit, for generating row address strobe signals to a memory, the row address strobe generator circuit comprising a multiplexer having a first input for receiving a row address strobe signal corresponding to data accesses, having a second input coupled to the output of the suspend refresh row address strobe circuit, and having a control input for receiving a signal corresponding to the suspend signal, for forwarding, to a memory, at least one row address strobe signal corresponding to the output of the suspend refresh row address strobe circuit responsive to the suspend signal.

8. The refresh controller circuit of claim 7, further comprising:

a column address strobe generator circuit, for generating at least one column address strobe signal to the memory in cooperation with the at least one row address strobe signal generated by the row address strobe generator circuit.

9. The refresh controller circuit of claim 8, further comprising:

a refresh queue counter circuit, having an enable input receiving a queuing enable signal, and having a clock input coupled to receive the refresh clock signal, for generating a refresh request signal responsive to receiving a selected number of pulses of the refresh clock signal; and

control logic, coupled to the refresh queue counter circuit, for controlling the row address strobe and column address strobe generator circuits to generate row address strobe and column address strobe signals, respectively, to effect a refresh operation responsive to the refresh request signal from the refresh queue counter circuit.

10. The refresh controller circuit of claim 9, wherein the control logic is also coupled to the suspend enable circuit, and controls the row address strobe greater to generate at least one row address strobe signal from the suspend refresh row address strobe circuit to effect refresh operations in suspend mode as indicated by the suspend signal.

11. The refresh controller circuit of claim 7, wherein the row address strobe generator circuit has a plurality of row address strobe outputs, for controlling refresh and access in a multiple-bank memory.

12. The refresh controller circuit of claim 11, wherein the suspend refresh row address strobe circuit generates a plurality of row address strobe signals, corresponding to the plurality of row address strobe outputs of the row address strobe generator circuit.

13. A computer system comprising:

a memory;

a memory bus coupled to said memory, comprising lines for communicating address, data, and control signals, the control signals comprising at least one row address strobe signal and at least one column address strobe signal;

a microprocessor unit, comprising;

a microprocessor having a processing unit operable to process digital data in accordance with computer instructions;

a memory controller, coupled to the microprocessor, and coupled to the memory via the memory bus, comprising;

an idle condition detector for detecting an idle condition responsive to absence of memory read or write requests from the microprocessor for a period of time;

a refresh clock circuit for generating a refresh clock signal;

a self refresh circuit having an input receiving the refresh clock signal, having an input for receiving a self refresh mode signal, and having an output for presenting the refresh clock signal responsive to the self refresh mode signal indicating that self refresh mode is not enabled, and for presenting a row address strobe disable state responsive to the self refresh mode signal indicating that self refresh mode is enabled;

a suspend enable circuit, having an input coupled to the idle condition detector and having an input for receiving a stop request signal, for generating a suspend signal responsive to receiving the stop request signal during an idle condition;

a suspend refresh row address strobe circuit having a first input coupled to the output of the self refresh circuit and having a second input coupled to receive the suspend signal, for generating at least one row address strobe signal corresponding to the output of the self refresh circuit responsive to receiving the suspend signal; and

a row address strobe generator circuit, for generating row address strobe signals to the memory, the row address strobe generator circuit comprising a multiplexer having a first input for receiving a row address strobe signal corresponding to data accesses requested by the microprocessor, having a second input coupled to the output of the suspend refresh row address strobe circuit, and having a control input for receiving a signal corresponding to the suspend signal, for forwarding, to the memory, at least one row address strobe signal corresponding to the output of the suspend refresh row address strobe circuit responsive to the suspend signal;

a peripheral processor unit coupled to said microprocessor unit and having circuitry for bidirectional data communication therewith;

a user input interface coupled to the peripheral processor unit; and

an output interface coupled to the peripheral processor unit.

14. The computer system of claim 13, further comprising:

a user input device coupled to the user input interface.

15. The computer system of claim 13, further comprising:

a docking station coupled to the user input interface; and

an input device connected to the docking station.

16. The computer system of claim 13, further comprising:

a display coupled to the output interface.

17. The computer system of claim 13, further comprising:

a docking station connected to the output interface; and

a display connected to the docking station.

18. The computer system of claim 13, wherein the user input interface, memory, output interface, peripheral processor unit, and microprocessor unit are attached to a printed wiring board having a substantially planar board element, and having conductors near a surface thereof for interconnecting the user input interface, memory, output interface, peripheral processor unit, and microprocessor unit.

19. The computer system of claim 13, wherein said microprocessor unit is implemented on a single integrated circuit device.

20. The computer system of claim 13, wherein the memory controller further comprises:

a column address strobe generator circuit, for generating at least one column address strobe signal to the memory in cooperation with the at least one row address strobe signal generated by the row address strobe generator circuit.

21. The computer system of claim 20, wherein the memory controller further comprises:

a refresh queue counter circuit, having an enable input receiving a queuing enable signal, and having a clock input coupled to receive the refresh clock signal, for generating a refresh request signal responsive to receiving a selected number of pulses of the refresh clock signal; and

control logic, coupled to the refresh queue counter circuit, for controlling the row address strobe and column address strobe generator circuits to generate row address strobe and column address strobe signals, respectively, to effect a refresh operation responsive to the refresh request signal from the refresh queue counter circuit.

22. The computer system of claim 21, wherein the control logic is also coupled to the suspend enable circuit, and controls to row address strobe generator to generate at least one row address strobe signal from the suspend refresh row address strobe circuit, to effect refresh operations in suspend mode as indicated by the suspend signal.

23. The computer system of claim 13, wherein the memory is arranged in a plurality of banks;

and wherein the row address strobe generator circuit has a plurality of row address strobe outputs, each associated with one of the plurality of banks of the memory.

24. The computer system of claim 23, wherein the suspend refresh row address strobe circuit generates a plurality of row address strobe signals, each corresponding to the plurality of row address strobe outputs of the row address strobe generator circuit.

25. A method of operating a computer system having a microprocessor and a memory, to control the refresh of the memory, comprising the steps of:

monitoring memory read requests and memory write requests;

responsive to the monitoring step detecting the absence of memory read requests and memory write requests over a period of time, and responsive to a suspend request signal from the microprocessor, generating a suspend acknowledge signal;

generating a refresh clock signal corresponding to a refresh period of the memory;

interrogating a control store to determine whether the memory is of self-refresh type;

responsive to the interrogating step determining that the memory is not of self-refresh type, applying the refresh clock signal to an input of a refresh row address strobe circuit;

responsive to the interrogating step determining that the memory is of self-refresh type, applying the refresh clock signal to an input of a refresh row address strobe circuit;

responsive to the interrogating step determining that the memory is of self-refresh type, blocking the refresh clock signal from the input of the refresh row address strobe circuit and instead applying an enable signal to the input of the refresh row address strobe circuit; and

responsive to the suspend acknowledge signal, controlling the refresh row address strobe circuit to generate at least one row address strobe signal to the memory corresponding to the signal applied at its input.

26. The method of claim 25, wherein the step of controlling the refresh row address strobe circuit comprises:

gating the signal applied at the input of the refresh row address strobe circuit with the suspend acknowledge signal to generate at least one gated refresh row address strobe signal; and

controlling a multiplexer, the multiplexer having a first input for receiving row address strobe signals corresponding to memory accesses by the microprocessor and having a second input for receiving the at least one gated refresh row address strobe signal, to select the at least one gated refresh row address strobe signal for application to the memory responsive to the suspend acknowledge signal.

27. The method of claim 25, further comprising:

counting periods of the refresh clock signal since a refresh operation;

responsive to the counting step, detecting a number of periods of the refresh clock signal exceed a limit, in combination with the monitoring step detecting that the absence of memory read requests and memory write requests over a period of time, refreshing the memory.

28. The method of claim 27, wherein the memory is of a CASbefore-RAS refresh type;

and wherein the step of refreshing the memory comprises;

applying a column address strobe signal to the memory; and

then applying a row address strobe signal to the memory.

29. The method of claim 28, further comprising:

responsive to the suspend acknowledge signal and to the interrogating step, determining that the memory is not of self-refresh type, applying at least one column address strobe signal to the memory prior in time to applying the at least one row address strobe signal to the memory corresponding to the refresh clock signal.