Multibus cached memory system
First Claim
Patent Images
1. In a computer system including;
- a plurality of buses, each bus serving at least one device, and each bus serving to communicate direct memory access read/write requests, data, and main memory addresses, from a device to a main memory which is tightly coupled to the devices;
a distributed cache memory system, comprising;
a first group of one or more devices requiring direct memory access;
a second group of one or more devices requiring direct memory access;
a first bus connecting said first group of devices directly to the main memory;
a first cache connected directly to said first bus and to the main memory;
a second bus connecting said second group of devices directly to the main memory;
a second cache connected directly to said second bus and to the main memory;
a cache memory control and arbitration unit coupled to said first and second cache, said first and second bus, and to said main memory for processing concurrent direct memory access requests from said first and said second bus.
3 Assignments
0 Petitions
Accused Products
Abstract
A method and apparatus for use in computer systems utilizes a memory chip employing multiple distributed SRAM caches directly linked to a single DRAM main memory block. Each cache is directly linked to a different bus. Each chip further contains a partially distributed arbitration and control circuit for implementing cache policy and arbitrating memory refresh cycles.
-
Citations
34 Claims
-
1. In a computer system including;
- a plurality of buses, each bus serving at least one device, and each bus serving to communicate direct memory access read/write requests, data, and main memory addresses, from a device to a main memory which is tightly coupled to the devices;
a distributed cache memory system, comprising;a first group of one or more devices requiring direct memory access; a second group of one or more devices requiring direct memory access; a first bus connecting said first group of devices directly to the main memory; a first cache connected directly to said first bus and to the main memory; a second bus connecting said second group of devices directly to the main memory; a second cache connected directly to said second bus and to the main memory; a cache memory control and arbitration unit coupled to said first and second cache, said first and second bus, and to said main memory for processing concurrent direct memory access requests from said first and said second bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- a plurality of buses, each bus serving at least one device, and each bus serving to communicate direct memory access read/write requests, data, and main memory addresses, from a device to a main memory which is tightly coupled to the devices;
-
9. A computer system including:
a first bus connected to a first group of one or more devices, a second bus connected to a second group of one or more devices, a main memory controller connected to the first and second bus, and a main memory element connected directly to the main memory controller and the first and second bus;
an improved main memory element, comprising;a first cache connected directly to said first bus and to the main memory element; a second cache connected directly to said second bus and to the main memory element; a cache memory control and arbitration unit coupled to said first and second cache, said first and second bus, the main memory element and to the main memory controller for processing concurrent direct memory access requests from the first and the second bus. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
-
17. A computer system including:
a first bus connected to a first group of one or more devices, a second bus connected to a second group of one or more devices, and a main memory connected directly to the first and second bus;
an improved main memory, comprising;a main memory arbitration and control unit connected to said first and second bus; at least one memory element connected to said main memory arbitration and control unit and to said first and said second bus said memory element containing; a) a main memory element; b) a first cache connected directly to said first bus and to said main memory element; c) a second cache connected directly to said second bus and to said main memory element; d) a cache memory control and arbitration unit coupled to said first and second cache, said first and second bus, said main memory element and to said main memory arbitration and control unit for processing concurrent direct memory access requests from the first and the second bus. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
-
25. An integrated memory circuit for use in a computer having first and second buses, comprising:
-
a DRAM directly coupled to said first and second buses; first and second memory caches for coupling to said first and second buses, each connected to cache data of selected addresses of said DRAM; and an arbitration and control circuit connected to said first and second memory caches and said DRAM for implementing a memory cache policy among said first and second memory caches and said DRAM and for processing concurrent direct memory access requests from said first and said second bus. - View Dependent Claims (26, 27, 28, 29, 30)
-
-
31. A memory system for use in a computer having a plurality of buses, comprising:
-
a plurality of integrated memory circuits, each including; a memory block directly coupled to said plurality of buses; first and second memory caches each for coupling to a respective one of said plurality of buses, each connected to cache data of selected addresses of said memory block; an arbitration and control circuit connected to said first and second memory caches and said memory block for implementing a memory cache policy among said first and second memory caches and said memory block; and a system level control and arbitration unit for arbitrating priority between concurrent memory access requests on different ones of said buses, for determining if a request for an address mapped to either memory or input/output is for memory, and for controlling which memory block is addressed. - View Dependent Claims (32, 33, 34)
-
Specification