Multibus cached memory system

• US 5,802,560 A
• Filed: 08/30/1995
• Issued: 09/01/1998
• Est. Priority Date: 08/30/1995
• Status: Expired due to Fees

• Current Assignee: Ramtron International Corporation (Infineon Technologies AG)
• Original Assignee: Ramtron International Corporation (Infineon Technologies AG)
• Inventors: Joseph, James Dean, Heisler, Dion Nickolas, Heisler, Doyle James
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Langjahr, David
• Application Number:
  US08/521,597
• Time in Patent Office: 1,098 Days
• Field of Search: 395/290, 395/403, 395/445, 395/460, 395/469, 395/473, 395/309, 395/449, 711/119
• US Class Current: 711/119
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 13/4018 with data-width conversion

Abstract

A method and apparatus for use in computer systems utilizes a memory chip employing multiple distributed SRAM caches directly linked to a single DRAM main memory block. Each cache is directly linked to a different bus. Each chip further contains a partially distributed arbitration and control circuit for implementing cache policy and arbitrating memory refresh cycles.

Claims

1. In a computer system including;

a plurality of buses, each bus serving at least one device, and each bus serving to communicate direct memory access read/write requests, data, and main memory addresses, from a device to a main memory which is tightly coupled to the devices;

a distributed cache memory system, comprising;

a first group of one or more devices requiring direct memory access;

a second group of one or more devices requiring direct memory access;

a first bus connecting said first group of devices directly to the main memory;

a first cache connected directly to said first bus and to the main memory;

a second bus connecting said second group of devices directly to the main memory;

a second cache connected directly to said second bus and to the main memory;

a cache memory control and arbitration unit coupled to said first and second cache, said first and second bus, and to said main memory for processing concurrent direct memory access requests from said first and said second bus.

2. The distributed cache memory system as set forth in claim 1, wherein:

said cache memory control and arbitration unit couples said first and second cache during a write request and uncouples said first and second cache during a read request.

3. The distributed cache memory system as set forth in claim 2, wherein:

said cache memory control and arbitration unit includes means for copying data written to an address located only in said main memory to said main memory;

said cache memory control and arbitration unit includes means for copying data written to an address located in said main memory and said first cache, to said main memory and said first cache;

said cache memory control and arbitration unit includes means for copying data written to an address located in said main memory and said second cache, to said main memory and said second cache; and

said cache memory control and arbitration unit includes means for copying data written to an address located in said main memory, said first cache and said second cache, to said main memory, said first cache and said second cache.

4. The distributed cache memory system as set forth in claim 2, wherein:

said cache memory control and arbitration unit includes means for responding to a read request communicated on said first bus and directed to an address located only in the main memory by copying said address and data from main memory to said first cache and transmitting said data from said first cache to said first bus;

said cache memory control and arbitration unit includes means for responding to a read request communicated on said first bus and directed to an address and data located both in the main memory and in said first cache by transmitting said data from said first cache to said first bus;

said cache memory control and arbitration unit includes means for responding to a read request communicated on said second bus and directed to an address located only in the main memory by copying said address and data from main memory to said second cache and transmitting said data from said second cache to said second bus; and

said cache memory control and arbitration unit includes means for responding to a read request communicated on said second bus and directed to an address and data located both in the main memory and in said second cache by transmitting said data from said second cache to second bus.

5. The distributed cache memory system as set forth in claim 1, wherein:

said cache memory control and arbitration unit includes means for determining priority for processing direct memory access requests from said first and said second bus.

6. The distributed cache memory system as set forth in claim 1, wherein:

said cache memory control and arbitration unit includes means for pipelining memory access requests.

7. The distributed cache memory system as set forth in claim 1, wherein:

said cache memory control and arbitration unit includes means for handling burst read requests.

8. The distributed cache memory system as set forth in claim 1, wherein:

said cache memory control and arbitration unit includes means for handling burst write requests.

9. A computer system including:

a first bus connected to a first group of one or more devices, a second bus connected to a second group of one or more devices, a main memory controller connected to the first and second bus, and a main memory element connected directly to the main memory controller and the first and second bus;

an improved main memory element, comprising;

a first cache connected directly to said first bus and to the main memory element;

a second cache connected directly to said second bus and to the main memory element;

a cache memory control and arbitration unit coupled to said first and second cache, said first and second bus, the main memory element and to the main memory controller for processing concurrent direct memory access requests from the first and the second bus.

10. The improved main memory element as set forth in claim 9, wherein:

said cache memory control and arbitration unit couples said first and second cache during a write request and uncouples said first and second cache during a read request.

11. The improved main memory element as set forth in claim 10, wherein:

said cache memory control and arbitration unit includes means for copying-data written to an address located only in the main memory element to the main memory element;

said cache memory control and arbitration unit includes means for copying data written to an address located in the main memory element and said first cache, to the main memory element and said first cache;

said cache memory control and arbitration unit includes means for copying data written to an address located in the main memory element and said second cache, to the main memory element and said second cache; and

said cache memory control and arbitration unit includes means for copying data written to an address located in the main memory element, said first cache and said second cache, to the main memory element, said first cache and said second cache.

12. The improved main memory element as set forth in claim 10, wherein:

said cache memory control and arbitration unit includes means for responding to a read request communicated on said first bus and directed to an address located only in the main memory element by copying said address and data from the main memory element to said first cache and transmitting said data from said first cache to said first bus;

said cache memory control and arbitration unit includes means for responding to a read request communicated on said first bus and directed to an address and data located both in the main memory element and in said first cache by transmitting said data from said first cache to said first bus;

said cache memory control and arbitration unit includes means for responding to a read request communicated on said second bus and directed to an address located only in the main memory element by copying said address and data from the main memory element to said second cache and transmitting said data from said second cache to said second bus; and

said cache memory control and arbitration unit includes means for responding to a read request communicated on said second bus and directed to an address and data located both in the main memory element and in said second cache by transmitting said data from said second cache to second bus.

13. The improved main memory element as set forth in claim 9, wherein:

said cache memory control and arbitration unit includes means for determining priority for processing direct memory access requests from said first and said second bus.

14. The improved main memory element as set forth in claim 9, wherein:

said cache memory control and arbitration unit includes means for pipelining memory access requests.

15. The improved main memory element as set forth in claim 9, wherein:

said cache memory control and arbitration unit includes means for handling burst read requests.

16. The improved main memory element as set forth in claim 9, wherein:

said cache memory control and arbitration unit includes means for handling burst write requests.

17. A computer system including:

a first bus connected to a first group of one or more devices, a second bus connected to a second group of one or more devices, and a main memory connected directly to the first and second bus;

an improved main memory, comprising;

a main memory arbitration and control unit connected to said first and second bus;

at least one memory element connected to said main memory arbitration and control unit and to said first and said second bus said memory element containing;

a) a main memory element;

b) a first cache connected directly to said first bus and to said main memory element;

c) a second cache connected directly to said second bus and to said main memory element;

d) a cache memory control and arbitration unit coupled to said first and second cache, said first and second bus, said main memory element and to said main memory arbitration and control unit for processing concurrent direct memory access requests from the first and the second bus.

18. The improved main memory as set forth in claim 17, wherein:

said cache memory control and arbitration unit couples said first and second cache during a write request and uncouples said first and second cache during a read request.

19. The improved main memory as set forth in claim 18, wherein:

said cache memory control and arbitration unit includes means for copying data written to an address located only in said main memory element to said main memory element;

said cache memory control and arbitration unit includes means for copying data written to an address located in said main memory element and said first cache, to said main memory element and said first cache;

said cache memory control and arbitration unit includes means for copying data written to an address located in said main memory element and said second cache, to said main memory element and said second cache; and

said cache memory control and arbitration unit includes means for copying data written to an address located in said main memory element, said first cache and said second cache, to said main memory element, said first cache and said second cache.

20. The improved main memory as set forth in claim 18, wherein:

said cache memory control and arbitration unit includes means for responding to a read request communicated on said first bus and directed to an address located only in the main memory element by copying said address and data from main memory element to said first cache and transmitting said data from said first cache to said first bus;

said cache memory control and arbitration unit includes means for responding to a read request communicated on said first bus and directed to an address and data located both in the main memory element and in said first cache by transmitting said data from said first cache to said first bus;

said cache memory control and arbitration unit includes means for responding to a read request communicated on said second bus and directed to an address located only in the main memory element by copying said address and data from the main memory element to said second cache and transmitting said data from said second cache to said second bus; and

said cache memory control and arbitration unit includes means for responding to a read request communicated on said second bus and directed to an address and data located both in the main memory element and in said second cache by transmitting said data from said second cache to second bus.

21. The improved main memory as set forth in claim 17, wherein:

said cache memory control and arbitration unit includes means for determining priority for processing direct memory access requests from said first and said second bus.

22. The improved main memory element as set forth in claim 17, wherein:

said cache memory control and arbitration unit includes means for pipelining memory access requests.

23. The improved main memory element as set forth in claim 17, wherein:

said cache memory control and arbitration unit includes means for handling burst read requests.

24. The improved main memory element as set forth in claim 17, wherein:

said cache memory control and arbitration unit includes means for handling burst write requests.

25. An integrated memory circuit for use in a computer having first and second buses, comprising:

a DRAM directly coupled to said first and second buses;

first and second memory caches for coupling to said first and second buses, each connected to cache data of selected addresses of said DRAM;

and an arbitration and control circuit connected to said first and second memory caches and said DRAM for implementing a memory cache policy among said first and second memory caches and said DRAM and for processing concurrent direct memory access requests from said first and said second bus.

26. The circuit of claim 25 wherein said first and second memory caches are first and second SRAM caches.

27. The circuit of claim 25 wherein said arbitration and control circuit is partially distributed on said chip.

28. The circuit of claim 25 wherein said first bus is a local bus and said second bus is a PCI bus.

29. The circuit of claim 25 wherein said first and second buses are data and address busses.

30. The circuit of claim 25 wherein said arbitration and control circuit arbitrates memory refresh cycles.

31. A memory system for use in a computer having a plurality of buses, comprising:

a plurality of integrated memory circuits, each including;

a memory block directly coupled to said plurality of buses;

first and second memory caches each for coupling to a respective one of said plurality of buses, each connected to cache data of selected addresses of said memory block;

an arbitration and control circuit connected to said first and second memory caches and said memory block for implementing a memory cache policy among said first and second memory caches and said memory block; and

a system level control and arbitration unit for arbitrating priority between concurrent memory access requests on different ones of said buses, for determining if a request for an address mapped to either memory or input/output is for memory, and for controlling which memory block is addressed.

32. The memory system of claim 31 wherein said memory block comprises a DRAM.

33. The memory system of claim 31 wherein said memory block is subdivided into a plurality of memory blocks, and wherein said first and second caches are each subdivided into cache parts, each of said cache parts being associated with a respective one of said memory blocks.

34. The memory system of claim 31 wherein each of said caches comprises two rows.