Information processing system and including a supplemental memory and method of operation

• US 5,802,562 A
• Filed: 03/22/1996
• Issued: 09/01/1998
• Est. Priority Date: 10/01/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kahle, James Allen
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Nguyen, Hiep T.
• Application Number:
  US08/620,862
• Time in Patent Office: 893 Days
• Field of Search: 395/444, 395/445, 395/250, 395/872, 395/452, 395/453, 395/464, 395/465, 395/473, 395/494, 711/122, 711/137, 711/138, 711/146
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency

Abstract

An information processing system and method of operation are provided. In response to a first instruction, a supplemental memory stores first information from a system memory. In response to a second instruction, a cache memory stores second information from the supplemental memory if the first information includes the second information and from the system memory otherwise.

Claims

1. An information processing system, comprising:

a processor;

a bus for communicating information;

a system memory coupled to the bus for storing at least a subset of the information;

a prefetch memory;

a cache memory, integral to said processor; and

circuitry coupled to the bus and to the prefetch and cache memories for;

storing first information from the system memory into the prefetch memory in response to a prefetch instruction requesting only the first information;

storing second information into the cache memory in response to a memory instruction requesting the second information, the second information being provided directly from the prefetch memory, independent of said bus, when the first information includes the second information, otherwise the second information being from the system memory without being added to the prefetch memory; and

maintaining coherency of the first information in the prefetch memory in response to address information from the bus.

2. The system of claim 1 wherein the cache memory is a blocking cache memory.

3. The system of claim 1 and further comprising a processor coupled to the memories for processing the instructions.

4. The system of claim 3 wherein the cache memory is integral with the processor.

5. The system of claim 3 wherein the prefetch memory and the circuitry are integral with the processor.

6. The system of claim 1 wherein the prefetch memory is smaller than the cache memory.

7. The system of claim 1 wherein the prefetch memory is smaller than the system memory.

8. The system of claim 1 wherein the circuitry invalidates the first information in the prefetch memory in response to a match between the address information from the bus and address information stored in the prefetch memory.

9. The system of claim 1 wherein the circuitry is for:

storing the second information into the cache memory in response to the memory instruction, independent of whether the prefetch memory is waiting for the first information from the system memory.

11. The system of claim 8 wherein said supplemental memory is a prefetch memory.

12. The system of claim 8 wherein said first instruction is a prefetch instruction.

13. The system of claim 8 wherein said cache memory is a blocking cache memory.

14. The system of claim 8 and further comprising a processor coupled to said memories for processing said instructions.

15. The system of claim 14 wherein said cache memory is integral with said processor.

16. The system of claim 14 wherein said supplemental memory and said circuitry are integral with said processor.

17. The system of claim 14 wherein said processor outputs a signal to designate said first instruction to said circuitry in response to said first instruction.

18. The system of claim 17 wherein said circuitry stores said first information into said supplemental memory in response to said signal.

19. The system of claim 8 wherein said supplemental memory is smaller than said cache memory.

20. The system of claim 8 wherein said supplemental memory is smaller than said system memory.

21. The system of claim 8 wherein said circuitry stores said first information into said supplemental memory in response to said first instruction having a first instruction type.

22. The system of claim 21 wherein said circuitry stores said second information into said cache memory in response to said second instruction having a second instruction type.

24. The system of claim 1 wherein the circuitry is for:

if the first information is absent from the cache memory, storing the first information from the system memory into the prefetch memory in response to the prefetch instruction.

25. The system of claim 24 wherein the circuitry is for:

only if the first information is absent from the cache memory, storing the first information from the system memory into the prefetch memory in response to the prefetch instruction.

10. An information processing system, comprising:

a processor;

a bus for communicating information;

a system memory couple to said bus for storing at least a subset of said information;

a supplemental memory;

a cache memory, integral to said processor; and

circuitry coupled to said bus and to said supplemental and cache memories for;

storing first information from said system memory into said supplemental memory in response to a first instruction requesting only said first information;

storing second information into said cache memory in response to a second instruction requesting said second information, said second information being provided directly from said supplemental memory, independent of said bus, when said first information includes said second information, otherwise said second information being from said system memory without being added to said supplemental memory; and

maintaining coherency of said first information in said supplemental memory in response to address information from said bus.

23. The system of claim 10 wherein said circuitry invalidates said first information in said supplemental memory in response to a match between said address information from said bus and address information stored in said supplemental memory.

26. The system of claim 10 wherein said circuitry is for:

storing said second information into said cache memory in response to said second instruction, independent of whether said supplemental memory is waiting for said first information from said system memory.

27. The system of claim 10 wherein said circuitry is for:

if said first information is absent from said cache memory, storing said first information from said system memory into said supplemental memory in response to said first instruction.

28. The system of claim 27 wherein said circuitry is for:

only if said first information is absent from said cache memory, storing said first information from said system memory into said supplemental memory in response to said first instruction.

37. The method of claim 23 wherein said step of maintaining coherency of said first information in said supplemental memory comprises said step of invalidating said first information in said supplemental memory in response to a match between said address information from said bus and address information stored in said supplemental memory.

29. A method of operating an information processing system, having a processor included therein, comprising the steps of:

communicating information through a bus;

storing at least a subset of said information in a system memory;

in response to a first instruction requesting only first information, storing said first information into a supplemental memory from said system memory;

in response to a second instruction requesting second information, directly storing, independent of said bus, said second information from said supplemental memory to a cache memory, integral to said processor, when said first information includes said second information, otherwise said second information being from said system memory without being added to said supplemental memory; and

maintaining coherency of said first information in said supplemental memory in response to address information from said bus.

30. The method of claim 29 wherein said step of storing said first information into said supplemental memory comprises the step of storing said first information into a prefetch memory.

31. The method of claim 29 wherein said step of storing said first information in response to said first instruction comprises the step of storing said first information in response to a prefetch instruction.

32. The method of claim 29 wherein said step of storing said second information into said cache memory comprises the step of storing said second information into a blocking cache memory.

33. The method of claim 29 and further comprising the step of outputting a signal in response to said first instruction.

34. The method of claim 33 wherein said step of storing said first information in response to said first instruction comprises the step of storing said first information in response to said signal.

35. The method of claim 29 wherein said step of storing said first information comprises the step of storing said first information in response to said first instruction having a first instruction type.

36. The method of claim 35 wherein said step of storing said second information comprises the step of storing said second information in response to said second instruction having a second instruction type.

38. The system of claim 29 wherein said step of storing said second information comprises the step of:

storing said second information into said cache memory in response to said second instruction, independent of whether said supplemental memory is waiting for said first information from said system memory.

39. The system of claim 29 wherein said step of storing said first information comprises the step of:

if said first information is absent from said cache memory, storing said first information from said system memory into said supplemental memory in response to said first instruction.

40. The system of claim 39 wherein said step of storing said first information comprises the step of:

only if said first information is absent from said cache memory, storing said first information from said system memory into said supplemental memory in response to said first instruction.