Computer system having cache prefetching amount based on CPU request types

• US 5,802,569 A
• Filed: 04/22/1996
• Issued: 09/01/1998
• Est. Priority Date: 04/22/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Genduso, Thomas Basilio, Vanderslice, Edward Robert
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/636,112
• Time in Patent Office: 862 Days
• Field of Search: 395/464, 395/421.03, 395/414, 395/440, 395/383, 395/584, 711/137, 711/113, 711/213, 711/204
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862

Abstract

A computer system is provided which includes a central processing unit (CPU), a main memory, cache memory and a cache controller. The CPU generates a first CPU control signal indicating whether a CPU request is a request for instruction or data and a second CPU control signal indicating whether a request is for retrieving information from memory or for storing information into the memory. The cache controller includes prefetch logic which is responsive to the type of request from the CPU, such as, for example, instruction or data, read or write, for determining the amount of data to be prefetched into the cache memory from the main memory.

Claims

1. A computer system, comprising

a main memory;

a central processing unit (CPU) generating a first CPU control signal indicating whether a request for information is a request for an instruction or a request for data and for generating a second CPU control signal indicating whether the request for information is for retrieving information from memory or for storing information into memory;

a cache memory system having a cache memory; and

a cache controller coupled to the cache memory and having registers and prefetch logic responsive to said first CPU control signal and said second CPU control signal for determining the amount of data to be prefetched into the cache memory from the main memory.

2. The computer system of claim 1, wherein said cache memory system comprises a hierarchical cache system and wherein said cache memory comprises a first high level cache memory and a second lower level cache memory.

3. The computer system of claim 1, wherein the cache controller includes a programmable prefetch control register for storing a value representing a programmable number of cache lines to be prefetched.

4. The computer system of claim 3, wherein said cache controller is responsive to the first CPU control signal indicating an instruction request for prefetching the number of cache lines represented by the value stored in the programmable prefetch control register.

5. The computer system of claim 1, wherein the cache controller includes a programmable prefetch control register for storing a value representing a programmable number of cache lines to be prefetched when the first CPU control signal indicates a data request and said second CPU control signal indicates that the data request is for retrieving information from the main memory.

6. The computer system of claim 5, wherein said cache controller is responsive to the first CPU control signal indicating a data request and the second to control signal indicating a data request for retrieving information from the main memory for prefetching the number of cache lines represented by the value stored in the programmable prefetch control register.

7. The computer system of claim 1, wherein said cache controller includes a programmable prefetch control register for storing a value representing a programmable number of cache lines to be prefetched when the first CPU control signal indicates a data request and said second CPU control signal indicates that the data request is for storing information into the main memory.

8. The computer system of claim 7, wherein said cache controller is responsive to the first CPU control signal indicating a data request and the second CPU control signal indicating a data request for storing information into the main memory for prefetching the number of cache lines represented by the value stored in the programmable prefetch control register.

9. The computer system of claim 1, wherein said cache controller includes a prefetch queue register set including a number of prefetch queue registers for storing a number of outstanding CPU requests for prefetching.

10. The computer system of claim 9, wherein each of said prefetch queue registers includes a first register field for storing the address of a respective CPU request and a second field for storing a request type based on the first CPU control signal and the second CPU control signal.

11. The computer system of claim 10, wherein said prefetch logic is responsive to the request type for determining whether the prefetching from the main memory is in ascending or descending order.

12. The computer system of claim 11, wherein the cache controller prefetches information from the main memory in an ascending order when the request type indicates a data request for retrieving information from the main memory, and wherein the cache controller prefetches information from the main memory in a descending order when the request type indicates a data request for storing information into the main memory.