Speculative cache snoop during DMA line update

• US 5,802,576 A
• Filed: 07/01/1996
• Issued: 09/01/1998
• Est. Priority Date: 07/01/1996
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Boddu, Jayabharat, Tzeng, Allan
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Lee, Felix B.
• Application Number:
  US08/677,011
• Time in Patent Office: 792 Days
• Field of Search: 395/464, 395/444, 395/445, 395/449, 395/450, 395/460, 395/473, 395/495, 395/421.03, 395/421.08, 395/421.09
• US Class Current: 711/146
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)

Abstract

A method and apparatus for facilitating the streaming of data over a system bus between a memory and a DMA device. This is accomplished by doing a speculative cache look-up, or snoop, on a next cache line during or immediately following the access of a current cache line. This is done for DMA transfers when the first DMA address is received, and before subsequent addresses are received. Thus, a determination of whether the cache line is in the cache can be done in advance, allowing the next cache line of data to stream over the bus to or from the cache without waiting for the next address from the system bus or requiring a rearbitration for the system bus.

Claims

1. A method for performing a DMA transfer in a system having a system bus, a main memory, a first and second level cache memory, and a dedicated second level cache bus, comprising the steps of:

performing a cache look-up for a cache line corresponding to a received DMA address;

storing at least 2 cache lines of DMA data in a buffer;

incrementing or decrementing said received DMA address to a next sequential cache line;

comparing said next sequential cache line to tags for a cache;

performing said comparing steps before a transfer for said next sequential cache line over said system bus;

redirecting a next DMA address to said main memory if said speculative cache look-up results in a cache miss;

releasing said system bus if said main memory is in use; and

comparing said next sequential cache line address to a page of said DMA address, and releasing said system bus if said page is not identical.

2. A microprocessor comprising:

a system bus I/O connected to a system bus;

a first level instruction cache;

a first level data cache;

a dedicated second level cache bus I/O connected to a second level cache bus;

a main memory bus I/O connected to a main memory bus;

cache look-up logic configured to determine whether a received DMA virtual address is in said caches;

speculative look-up logic configured to cause a speculative look-up of a next sequential cache line;

a buffer configured to store at least two cache lines of DMA data;

redirecting logic configured to issue a command to redirect a DMA access to a main memory upon a speculative cache look-up miss;

page logic configured to compare said next sequential cache line address to a page of said DMA address; and

bus release logic configured to release said system bus if said page is not identical to a page of said next sequential cache line address.

3. A computer system comprising:

a system bus;

a DMA device coupled to said system bus;

a main memory;

a microprocessor coupled to said system bus, including

cache look-up logic configured to determine whether a received DMA address is in a cache,

speculative look-up logic configured to cause a speculative look-up of a next sequential cache lines,

page logic configured to compare said next sequential cache line address to a page of said DMA address, and

bus release logic configured to release said system bus if said page is not identical to a page of said next sequential cache line address;

a first level cache integrated on said microprocessor and a second level cache coupled to said microprocessor by a dedicated cache bus; and

a memory bus coupling said memory to said microprocessor.