Multi-processing cache coherency protocol on a local bus
First Claim
1. A computer system comprising:
- a local bus;
a plurality of caches coupled to the local bus, at least one of which is a write-back cache;
a main memory coupled to the local bus;
at least one processor coupled to the local bus;
a bus master coupled to the local bus, wherein a cache of the plurality of caches is operable to generate a plurality of signals which include;
a shared signal generated in response to a data element that is snooped on the first local bus being present in the cache; and
a snoop-busy signal that is active when the cache is in the process of searching for the data element being snooped on the local bus; and
a circuit directly coupled to each of the multiple caches that receives the snoop-busy signal from each of the multiple caches and transmits a done signal on the local bus in response.
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Abstract
A computer system maintaining cache coherency among a plurality of caching devices coupled across a local bus includes a bus master, a memory, and a plurality of cache complexes, all coupled to the local bus. When the bus master requests a read or write with the memory, the cache complexes snoop the transaction. Each cache complex asserts a busy signal during the snooping process. A detection circuit detects when the busy signals have been de-asserted and asserts a done signal. If one of the snoops results in a cache hit to a dirty line, the respective cache complex asserts a dirty signal. If one of the snoops results in a cache hit to a clean line, the respective cache complex asserts a clean signal. If the memory detects a simultaneous assertion of the dirty signal and the done signal, it halts the transaction request from the bus master.
78 Citations
12 Claims
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1. A computer system comprising:
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a local bus; a plurality of caches coupled to the local bus, at least one of which is a write-back cache; a main memory coupled to the local bus; at least one processor coupled to the local bus; a bus master coupled to the local bus, wherein a cache of the plurality of caches is operable to generate a plurality of signals which include; a shared signal generated in response to a data element that is snooped on the first local bus being present in the cache; and a snoop-busy signal that is active when the cache is in the process of searching for the data element being snooped on the local bus; and a circuit directly coupled to each of the multiple caches that receives the snoop-busy signal from each of the multiple caches and transmits a done signal on the local bus in response. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for operating multiple caches coupled to a local bus in a computer system, including at least one write-back cache, comprising the steps of:
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performing a snoop operation, wherein a bus master component initiates a search for a data element in each of the multiple caches; transmitting a shared signal from each of the multiple caches to the bus master in response to the data element being found in the cache; asserting a snoop busy signal for each of the multiple caches that is searching for a data element; sensing a snoop busy signal from the multiple caches; and transmitting a snoop done (SDONE) signal to each of caches and to the bus master in response to the states of the snoop busy signals. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification