Explicit coherence using split-phase controls

• US 5,802,582 A
• Filed: 09/10/1996
• Issued: 09/01/1998
• Est. Priority Date: 09/10/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pattnaik, Pratap Chandra, Ekanadham, Kattamuri, Lim, Beng-Hong
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Nguyen, Hiep T.
• Application Number:
  US08/711,750
• Time in Patent Office: 721 Days
• Field of Search: 395/726, 711/142, 711/143, 711/144, 711/145, 711/152, 711/157, 711/173, 711/141, 711/169, 711/148, 711/5
• US Class Current: 711/152
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0837 with software control, e.g. non-cacheable data
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/1056 Simplification
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A method and apparatus for maintaining cache coherence in a shared memory multiprocessor system, where cache coherence is preserved between lock acquires and releases rather than at every single memory load and store. With this invention, a Global Lock Manager (GLM) keeps track of the status of locked ranges without the need to maintain a list of individual processors in the system. Further a Recently Acquired Lock Manager (RALM) keeps track of the status of locked ranges within a processing node to reduce the need to communicate with a GLM.

Claims

1. A coherence object controller for operation with a multiprocessor system for interleaving accesses to a plurality of objects while preventing corruption of said objects, said coherence object controller comprising:

a. a Recently Acquired Lock Manager (RALM) for receiving explicit coherence commands from one of said processors, wherein said command to acquire a range of memory addresses is submitted by one of said processors, wherein each of said explicit coherent commands can be either an acquire command or a release command, said acquire command being a command to acquire a range of memory addresses in a write or read only mode, said release command being a command to release a range of memory addresses, and said recently acquired lock manager for generating lock commands in response to said explicit coherence commands, said RALM receiving responses to said lock commands and setting completion bits in a completion bit vector maintained in said one processor, each completion bit in said completion bit vector indicating completion of a corresponding one of said explicit coherence commands; and

b. a Global Lock Manager (GLM) for receiving said lock commands from said RALM and for generating said responses granting or denying said lock commands from said RALM, wherein each of said lock commands indicates either a write or a read only mode, wherein said RALM and GALM prevent multi-processors from simultaneously modifying said objects by granting said lock commands in a write mode to only a single processor at a time,

wherein said command to acquire a range of memory addresses is submitted by one of said processors, wherein said one processor is permitted to continue execution of other commands after submission of said acquire command and without waiting for completion of said acquire command, and wherein said one processor checks for the setting of a corresponding bit in said completion bit vector before it accesses said range specified in said acquire command.

2. The controller as recited in claim 1, wherein a reference count is used to indicate release of said first range by all other of said processors.

3. The controller as recited in claim 1, wherein each processor issuing an explicit coherence write command with a first range of addresses waits for release of said first range by all other of said processors before writing to said first range.

4. A coherence object controller for operation with a multiprocessor system for interleaving accesses to a plurality of objects while preventing corruption of said objects, said coherence object controller comprising:

a. a Recently Acquired Lock Manager (RALM) for receiving explicit coherence commands from one of said processors, wherein each of said explicit coherence commands can be either an acquire command or a release command, said acquire command being a command to acquire a range of memory addresses in write or a read only mode, said release command being a command to release a range of memory addresses, and for generating lock commands in response to said explicit coherence commands, said RALM receiving responses to said lock commands and setting completion bits in a a completion bit vector indicating completion of a corresponding one of said explicit coherence commands; and

b. a Global Lock Manager (GLM) in each node of said system for receiving said lock commands from said RALM and for generating said responses granting or denying said lock commands from said RALM, wherein each of said lock commands indicates either a write or a read only mode, wherein said RALM and GLM prevent multiprocessors from simultaneously modifying said objects by granting said lock commands in a write mode to only a single processor at a time, wherein each GLM maintains locks for a corresponding assigned range of addresses,

wherein said command to acquire a range of memory addresses is submitted by one of said processors, where said one processor is permitted to continue execution of other commands after submission of said acquire command and without waiting for completion of said acquire command, and wherein said one processor checks for the setting of a corresponding bit in said completion bit vector before it accesses said range specified in said acquire command.

5. A coherence object controller for operation with a multiprocessor system for interleaving accesses to a plurality of objects while preventing corruption of said objects, said coherence object controller comprising:

a. means for executing explicit coherence commands received from processors of said multiprocessor system, wherein each of said explicit coherent commands can be either an acquire or a release command, said acquire command being a command to acquire a range of memory addresses in a write or read only mode, said release command being a command to release a range of memory addresses;

b. means for indicating completion of execution of said explicit coherence commands wherein said means for indicating completion of said explicit coherence commands is a completion bit vector maintained in a register in each of said processors;

c. means for holding any first range of addresses by any one of said processors in a write or read only mode upon indication of completion of one of said explicit coherence commands from said one processor, said mode being a write mode if said one explicit coherence command is an acquire write command, and said mode being a read only mode if said one explicit coherence command is an acquire read only command; and

d. means for dropping any second range of addresses by any one of said processors upon indication of completion by latter said one processor of an explicit coherence command, of said explicit coherence commands, if latter said explicit command is a release command;

wherein said command to acquire a range of memory addresses is submitted by one of said processors, wherein said one processor is permitted to continue execution of other commands after submission of said acquire command and without waiting for completion of said acquire command, and wherein said one processor checks for the setting of a corresponding bit in said completion bit vector before it accesses said range specified in said acquire command.