Method and apparatus for determining a desirable directory/data block ratio in a cache memory
First Claim
1. A method for dynamically balancing storage allocations in a computer system that includes cache memory that is accessible from plural computer modules, each computer module including local memory for storage of data blocks, the cache memory including a first portion for storing plural data blocks and a second portion for storing directory entries, each directory entry including information regarding a validity status of an associated data block, said method comprising the steps of:
- a) maintaining a first record of a number of cache misses over a time period, each cache miss occurring when a computer module does not find a desired data block resident in said cache memory;
b) maintaining a second record of a number of false invalidations over a time period, each false invalidation occurring when a desired data block is resident in a computer module'"'"'s local memory but a directory entry for said desired data block with a validity status indication therefor, is absent from said cache memory; and
c) employing said first record and second record to adjust a ratio of size allocations of said first portion and second portion so as to reduce at least one of said number of false invalidations and number of cache misses.
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Abstract
A data processing system dynamically balances allocation of storage areas in a shared coupling facility that is devoted to storage of directory entries and data blocks. Each directory entry includes information regarding the validity of a data block that is locally stored by one or more processor modules in the data processing system. The system includes a coupling facility having a cache memory wherein a first portion is allocated to storage of data blocks and a second portion is allocated to storage of directory entries. Each directory entry, associated with a data block, indicates the validity or invalidity of data contained in a copy of the data block maintained by a connected computer module in its local memory. Each computer module, upon requiring a first data block and determining that (i) the first data block is present in its local memory (i.e., a buffer "hit"), but (ii) is not marked valid and (iii) is not present in the coupling facility (i.e., a cache "miss"), accesses the first data block from a disk store, even though the first data block in its local memory may be valid. A memory allocation procedure controls the sizes of the first portion and second portion of the cache memory. The procedure (i) maintains a record, per unit of time, of a number of cache "miss" occurrences, (i.e., a cache "miss" rate) and an estimate of the number of false invalidation occurrences (i.e., a false invalidation rate); derives a first order derivative of the sum of cache miss-rate and the estimated false invalidation rate and (iii) employs the derivative to adjust the sizes of the first portion and second portion of the cache memory so as to minimize the sum of the expected miss and false invalidation rate values.
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Citations
21 Claims
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1. A method for dynamically balancing storage allocations in a computer system that includes cache memory that is accessible from plural computer modules, each computer module including local memory for storage of data blocks, the cache memory including a first portion for storing plural data blocks and a second portion for storing directory entries, each directory entry including information regarding a validity status of an associated data block, said method comprising the steps of:
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a) maintaining a first record of a number of cache misses over a time period, each cache miss occurring when a computer module does not find a desired data block resident in said cache memory; b) maintaining a second record of a number of false invalidations over a time period, each false invalidation occurring when a desired data block is resident in a computer module'"'"'s local memory but a directory entry for said desired data block with a validity status indication therefor, is absent from said cache memory; and c) employing said first record and second record to adjust a ratio of size allocations of said first portion and second portion so as to reduce at least one of said number of false invalidations and number of cache misses. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory device including a procedure for dynamically balancing storage allocations when used in conjunction with a computer system, said computer system including cache memory that is accessible from plural computer modules, each computer module including local memory for storage of data blocks, the cache memory including a first portion for storing plural data blocks and a second portion for storing directory entries, each directory entry including information regarding a validity status of an associated data block, said memory device comprising:
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means for maintaining a first record of a number of cache misses over a time period in respect of said cache memory, each cache miss occurring when a computer module does not find a desired data block resident in said cache memory; means for maintaining a second record of a number of false invalidations over a time period, each false invalidation occurring when a desired data block is resident in a computer module'"'"'s local memory but a directory entry for said desired data block with a validity status indication therefor, is absent from said cache memory; and means for controlling a processor present in said computer system to employ said first record and second record to adjust a ratio of size allocations of said first portion and second portion so as to reduce at least one of said number of false invalidations and number of cache misses. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A data processing system including means for dynamically balancing storage allocations of a cache memory in a shared cache memory, the cache memory storing directory entries and data blocks, each directory entry including information regarding validity of at least a data block locally stored with one or more processor modules in said data processing system, said data processing system comprising:
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a cache memory with a first portion allocated for storage of data blocks and a second portion allocated for storage of directory entries, each directory entry indicating a validity status indication for data contained in a data block; plural computer modules coupled to said cache memory, each having local memory for storage of data blocks, a processor module, upon requiring a first data block and determining that (i) said first data block is present in local memory in said processor module, (ii) and neither a directory entry corresponding to said first data block or a copy of said first data block is present in said cache memory (i.e., a cache miss), performing an access of said first data block from a disk store, even though said first data block in local memory may be valid, (i.e., a false invalidation); and processor means associated with said coupling facility for controlling a ratio of sizes of said first portion and second portion by a memory allocation procedure, said procedure (i) maintaining a record of a number of cache miss occurrences (i.e., a cache miss rate) and of a number of false invalidation occurrences (i.e., a false invalidation rate) (ii) deriving a function of a sum of said cache miss rate and said false invalidation rate and (iii) employing said function to adjust said ratio of said sizes of said first portion and second portion. - View Dependent Claims (17, 18, 19, 20, 21)
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Specification