Structure having cavities and process for producing such a structure

• US 5,804,086 A
• Filed: 08/01/1996
• Issued: 09/08/1998
• Est. Priority Date: 01/26/1994
• Status: Expired due to Term

• Current Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Original Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Inventors: Bruel, Michel
• Primary Examiner(s): Breneman, R. Bruce
• Assistant Examiner(s): ALANKO, ANITA KAREN
• Application Number:
  US08/676,228
• Time in Patent Office: 768 Days
• Field of Search: 216/34, 216/36, 216/62, 216/65, 216/2, 216/33, 216/52, 216/56, 216/88, 156/631.1, 156/647.1, 437/24, 438/53, 438/692, 438/705, 438/707, 438/924
• US Class Current: 216/33
• CPC Class Codes: B81C 1/00047 Cavities
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/4803 Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks H01L21/4846 takes precedence; printed circuit boards H05K1/00
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 24/26 Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01058 Cerium [Ce]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/07802 not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

This process for producing a structure incorporating a substrate (2), a thin surface film (16) made from a non-conducting material joined to one face (1) of the substrate (2), said substrate (2) having cavities (10) flush with said face (1), comprises the following successive stages:

etching cavities (10) in one face (1) of a substrate, the cavities having in the plane of the substrate face at least one dimension which is a function of the thickness of the surface film, in order to correctly secure the latter,

joining a non-conducting material wafer (12) to the face (1) of the substrate (2),

thinning the wafer (12) to obtain the thin surface film.

Claims

1. A process for producing a structure having a substrate, a thin surface film of a non-conducting material, joined to one face of the substrate, said substrate having cavities flush with said face, the process comprising the following successive steps:

etching cavities in one face of a substrate, the cavities having in the plane of the substrate face at least one dimension which is a function of the thickness of the surface film in order to correctly secure the latter;

joining a non-conducting material wafer having a solid portion, an intermediate layer and a thin film to the face of the substrate wherein said thin film is adjacent said face of the substrate;

thinning the wafer to obtain a thin surface section, the thinning of the wafer being obtained by separating the film of the solid portion from the intermediate layer;

wherein the intermediate layer is a layer of microbubbles between the thin film and the solid portion and obtained by prior implantation of gas in the wafer, and the separation of the film is brought about by cleaving the wafer along a cleaving plane defined by the microbubble layer.

3. Process according to claim 1 or claim 2, characterized in that each cavity has in the plane of the face of the substrate at least one dimension l equal to or smaller than the maximum value l_o proportional to the thickness of the surface film.

4. Process according to claim 3, characterized in that the wafer is of silicon and has a thickness e_o, giving l_o =10.e_o.

5. Process according to claim 1 or claim 2, characterized in that the cavities are longitudinal trenches.

2. A process for producing a structure having a substrate, a thin surface film of a non-conducting material, joined to one face of the substrate, said substrate having cavities flush with said face, the process comprising the following successive steps:

etching cavities in one face of a substrate, the cavities having in the plane of the substrate face at least one dimension which is a function of the thickness of the surface film in order to correctly secure the latter;

joining a non-conducting material wafer having a solid portion, an intermediate layer and a thin film to the face of the substrate wherein said thin film is adjacent said face of the substrate;

thinning the wafer to obtain a thin surface section, the thinning of the wafer being obtained by separating the film of the solid portion from the intermediate layer;

wherein the intermediate layer is formed by prior implantation of gas in the wafer and annealing, and the separation of the film is brought about by chemical etching of said intermediate layer.

6. A process for producing a structure having a substrate, a thin surface film of a non-conducting material, joined to one face of the substrate, said substrate having cavities flush with said face, the process comprising the following successive steps:

etching cavities in one face of a substrate, the cavities having in the plane of the substrate face at least one dimension which is a function of the thickness of the surface film in order to correctly secure the latter;

joining a non-conductive material wafer having a solid portion, an intermediate layer and a thin film to the face of the substrate wherein said thin film is adjacent said face of the substrate;

thinning the wafer to obtain a thin surface section, the thinning of the material wafer being brought about by mechanical, chemical and/or mechano-chemical abrasion of a portion of the wafer.

7. A process according to claim 6, wherein each cavity has in the plane of the face of the substrate at least one dimension l, equal to or smaller than the maximum value l_o proportional to the thickness of the surface film.

8. A process according to claim 7, wherein the wafer is made of silicon and has a thickness e_o, giving l_o =10.e_o.

9. A process according to claim 6, wherein the cavities are longitudinal trenches.

10. Process according to claim 6, characterized in that the thinning of the wafer is brought about by grinding.

11. Process according to claim 6, characterized in that the thinning of the wafer is obtained by the polishing thereof.