Process for producing a semiconductor package

• US 5,804,422 A
• Filed: 09/13/1996
• Issued: 09/08/1998
• Est. Priority Date: 09/20/1995
• Status: Expired due to Fees

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: Yoda, Toshihisa, Shimizu, Mitsuharu
• Primary Examiner(s): PICARDAT, KEVIN M
• Application Number:
  US08/713,551
• Time in Patent Office: 725 Days
• Field of Search: 438/111, 438/121, 438/122, 438/123, 438/125
• US Class Current: 438/125
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 Multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA

Abstract

A semiconductor package is produced by the following steps. A plurality of circuit boards are prepared, each board having an opening for forming a cavity and a surface providing with a circuit pattern having bonding sections at a peripheral area of the opening. The bonding sections of the respective circuit boards are covered with protective films. A laminated body is formed by laminating the plurality of circuit boards by means of adhesive sheets arranged between the respective circuit boards. Upper and lower substrates are also laminated on upper and lower surfaces of the plurality of circuit boards, respectively, by means of adhesive sheets to close the cavity. The protective films are subsequently removed from the bonding sections of the respective circuit boards of the laminated body.

Claims

1. A process for producing a semiconductor package, said process comprising the following steps of:

preparing a plurality of circuit boards, each having an opening for forming a cavity and a surface providing with a circuit pattern having bonding sections at a peripheral area of said opening;

coating said bonding sections of the respective circuit boards with protective films;

forming a laminated body by laminating said plurality of circuit boards by means of adhesive sheets arranged between said respective circuit boards so that said cavity is defined by said openings and said bonding sections of the respective circuit boards are exposed in said cavity, and laminating first and second substrates on upper and lower surfaces of said plurality of circuit boards, respectively, by means of adhesive sheets to close said cavity;

providing said laminated body with through-holes for connecting said circuit patterns to external terminals and plating said through-holes with conductive metal;

forming an opening to at least one of said first and second substrates so that said cavity is opened; and

removing said protective films from said bonding sections of the respective circuit boards of the laminated body.

2. A process as set forth in claim 1, wherein both of said first and second substrate are formed with openings so that said cavity is opened at both of upper and lower surfaces of said laminated body.

3. A process as set forth in claim 1, wherein after said bonding sections of the circuit board is coated by said protective films and said surface of the circuit board is coated with a resist to make said surface flat, said plurality of circuit boards are laminated by means of adhesive sheets arranged between said respective circuit boards.

4. A process as set forth in claim 1, wherein said protective films comprise a photoresist.

5. A process for producing a semiconductor package, said process comprising the following steps of:

preparing a plurality of circuit boards, each having an opening for forming a cavity and a surface providing with a circuit pattern having bonding sections at a peripheral area of said opening;

coating said surfaces of the respective circuit boards with photoresist;

optically exposing part of said photoresist on the respective circuit board in such a manner that protective films of said photoresist, which can be removed in a subsequent step, are formed on said bonding sections;

forming a laminated body by laminating said plurality of circuit boards by means of adhesive sheets arranged between said respective circuit boards so that said cavity is defined by said openings and said bonding sections of the respective circuit boards are exposed in said cavity, and laminating first and second substrates on upper and lower surfaces of said plurality of circuit boards, respectively, by means of adhesive sheets to close said cavity;

providing said laminated body with through-holes for connecting said circuit patterns to external terminals and plating said through-holes with conductive metal;

forming an opening to at least one of said first and second substrates so that said cavity is opened; and

removing said protective films from said bonding sections of the respective circuit boards of the laminated body.

6. A process as set forth in claim 5, wherein both of said first and second substrate are formed with openings so that said cavity is opened at both of upper and lower surfaces of said laminated body.

7. A process as set forth in claim 5, wherein a negative type photoresist is used as said photoresist and part of said photoresist except on said bonding sections of the circuit pattern are exposed, before said plurality of circuit boards are laminated.

8. A process as set forth in claim 5, wherein a positive type photoresist is used as said photoresist and part of said photoresist on said bonding sections of the circuit pattern are exposed, before said plurality of circuit boards are laminated.

9. A process as set forth in claim 5, wherein said protective films are removed from said bonding sections of the respective circuit boards by dissolving said protective films with a solvent.