Method for charge enhanced defect breakdown to improve yield and reliability

• US 5,804,459 A
• Filed: 11/15/1996
• Issued: 09/08/1998
• Est. Priority Date: 11/15/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bolam, Ronald Jay, Gregoritsch, Albert John Jr.
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/751,151
• Time in Patent Office: 662 Days
• Field of Search: 438/5, 438/10, 438/11, 438/12, 438/17, 438/18
• US Class Current: 438/12
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

According to the present invention, an improved method for locating particle contamination during the integrated circuit manufacturing process is disclosed. The integrated circuit wafer is grounded and then exposed to an electron beam to create an enhanced electrical potential in any conducting or semi-conducting particles embedded in the layered wafer. The embedded particle will begin to accumulate an electrical charge and will reach a certain electrical potential based on the size and composition of the particle as well as the length of exposure to the electron beam. After a sufficient charge has been accumulated in the embedded particle, the wafer is subjected to burn-in testing. Since the particles embedded in the wafer have been previously exposed to the electron beam, the standard voltages applied during burn-in testing will force a certain number of embedded particles to suffer accelerated breakdown. After the defects have occurred and have been located, on-chip fuses can be used to re-route the circuits. As a final step, the wafer is annealed to remove any residual charge in any remaining particle defects not found by the present invention.

Claims

1. A method of improving integrated circuit reliability, the method comprising the steps of:

providing a layered wafer, the wafer comprising;

a substrate having a plurality of diffused regions;

at least one overlying conductive layer;

at least one overlying non-conductive layer, wherein the at least one non-conductive layer contains at least one embedded electrically-isolated conductive particle,

and wherein the substrate, the plurality of diffused regions, and the at least one conductive layer are all electrically grounded; and

exposing the wafer to an electron beam of a pre-determined energy level for a pre-determined period of time, thereby increasing the electrical potential of the at least one embedded electrically-isolated conductive particle.

2. The method of claim 1 further comprising the step of performing burn-in testing on the wafer.

3. The method of claim 1 further comprising the step of annealing the wafer.

4. The method of claim 1 wherein the pre-determined energy level is 25 keV.

5. The method of claim 1 wherein the pre-determined period of time is six minutes.

6. The method of claim 1 wherein the pre-determined period of time is twelve minutes.

7. The method of claim 1 wherein the pre-determined energy level is 25 keV and the given period of time is six minutes.

8. The method of claim 1 further comprising the step of using a redundant circuit to bypass an inoperative circuit path.

9. The method of claim 1 wherein the substrate contains N-well or P-well sources, drains, and junctions.

10. The method of claim 1 further comprising elevating the temperature of the wafer to enhance current dissipation.

11. A method of improving integrated circuit reliability, the method comprising the steps of:

providing a layered wafer, the wafer comprising;

a substrate having a plurality of diffused regions;

at least one overlying conductive layer;

at least one overlying non-conductive layer, wherein the at least one non-conductive layer contains at least one embedded electrically-isolated conductive particle,

and wherein the substrate, the purality of diffused regions, and the at least one condutive layer are all electrically grounded;

exposing the wafer to an electron beam with an energy level of 25 keV for a period of six minutes, thereby increasing the electrical potential of the at least one embedded electrically-isolated conductive particle;

performing burn-in testing on the wafer; and

annealing the wafer to remove any excess electrical potential from the wafer.

12. The method of claim 11 further comprising the step of using a redundant circuit to bypass an inoperative circuit path.

13. The method of claim 11 wherein the substrate contains N-well or P-well sources, drains, and junctions.

14. The method of claim 11 further comprising elevating the temperature of the wafer to enhance current dissipation.

15. A method of improving integrated circuit reliability, the method comprising the steps of:

providing a layered wafer, the wafer comprising;

a substrate having a plurality of diffused regions;

at least one overlying conductive layer;

at least one overlying non-conductive layer, wherein the at least one non-conductive layer contains at least one embedded electrically-isolated conductive particle,

and wherein the substrate, the purality of diffused regions, and the at least one condutive layer are all electrically grounded;

exposing the wafer to an electron beam with an energy level of 25 keV for a period of six minutes, thereby increasing the electrical potential of the at least one embedded electrically-isolated particle;

elevating the temperature of the wafer to enhance current dissipation;

performing burn-in testing on the wafer;

using a redundant circuit to bypass an inoperative circuit path; and

annealing the wafer to remove any excess electrical potential from the wafer.