Stacked capacitor DRAM structure featuring a multiple crown shaped polysilicon lower electrode

• US 5,804,852 A
• Filed: 06/16/1997
• Issued: 09/08/1998
• Est. Priority Date: 09/09/1996
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Yang, Fu-Liang, Jeng, Erik S.
• Primary Examiner(s): Crane, Sara W.
• Application Number:
  US08/876,914
• Time in Patent Office: 449 Days
• Field of Search: 257/296, 257/303, 257/306, 257/307, 257/308, 257/309, 437/919, 437/47, 437/52, 365/149
• US Class Current: 257/308
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments

Abstract

A multiple crown shaped polysilicon structure, used for a lower electrode of a DRAM stacked capacitor structure, has been developed. The multiple crown shaped, lower electrode, is formed overlying, and contacting a polysilicon fill layer, that is located between insulator encapsulated polycide gate structures. The polysilicon fill layer, in turn, contacts an underlying source/drain region of a transfer gate transistor. The multiple crown shaped lower electrode is comprised vertical polysilicon shapes, connected to an underlying, horizontal polysilicon shape, with the horizontal polysilicon shape overlying the polysilicon fill layer. One to three, vertical polysilicon shapes, are used on each side of the multiple crown shaped lower electrode.

Claims

1. A stacked capacitor structure, dynamic random access memory, (DRAM), device, with multiple crown shaped, polysilicon, lower electrodes, on a semiconductor structure, comprising:

a first field oxide region in said semiconductor substrate;

a second field oxide region in said semiconductor substrate;

a first silicon nitride capped, polycide gate structure, on said first filed oxide region;

a fourth silicon nitride capped, polycide gate structure, on said second field oxide region;

a first boro-phosphosilicate glass, (BPSG), pillar, on said first silicon nitride capped, polycide gate structure, and a fourth BPSG pillar on said fourth silicon nitride capped, polycide gate structure, with said first BPSG pillar, and with said fourth BPSG pillar, narrower in width than the underlying, silicon nitride capped, polycide gate structures, and between about 1000 to 7000 Angstroms in height;

a second silicon nitride capped, polycide gate structure, and a third silicon nitride capped, polycide gate structure, on said semiconductor substrate, between said first field oxide region, and said second field oxide region;

a second BPSG pillar, on said second silicon nitride capped, polycide gate structure, and a third BPSG pillar, on said third silicon nitride capped, polycide gate structure, with said second BPSG pillar, and with said third BPSG pillar narrower in width than the underlying silicon nitride capped, polycide gate structures, and between about 3000 to 10000 Angstroms in height;

silicon nitride, insulator spacers on sidewalls of silicon nitride capped, polycide gate structures;

a first source/drain region in an area of said semiconductor substrate, between said first field oxide region and said second silicon nitride capped, polycide gate structure;

a second source/drain region in an area of said semiconductor substrate, between said second silicon nitride capped, polycide gate structure and said third silicon nitride capped, polycide gate structure;

a third source/drain region in an area of said semiconductor substrate, between said third silicon nitride capped, polycide gate structure and said second field oxide region;

a first polysilicon fill, between said first silicon nitride capped, polycide gate structure and said second silicon nitride capped, polycide gate structure, contacting said first source/drain region, with said first polysilicon fill recessed to a level in which the top surface of said first polysilicon fill is equal to, or below, the top surface of said second silicon nitride capped, polycide gate structure, and of said first silicon nitride capped, polycide gate structure;

a second polysilicon fill, between said second silicon nitride capped, polycide gate structure and said third silicon nitride capped, polycide gate structure, contacting said second source/drain region, with the top surface of said second polysilicon fill at a height above the top surface of said second BPSG pillar, and of said third BPSG pillar;

a third polysilicon fill, between said third silicon nitride capped, polycide gate structure and said fourth silicon nitride capped, polycide gate structure, contacting said third source/drain region, with said third polysilicon fill recessed to a level in which the top surface of said third polysilicon fill is equal to, or below, the top surface of said third silicon nitride capped, polycide gate structure, and of said fourth silicon nitride capped, polycide gate structures;

a bit line contact structure between said second BPSG pillar and said third BPSG pillar, contacting said second polysilicon fill;

silicon oxide insulator spacers on sides of said bit line contact structure;

an insulator shape directly overlying said bit line contract structure;

a first, multiple crown, polysilicon lower electrode, overlying said insulator shape, on said bit line contact structure, and overlying said first BPSG pillar, and said second BPSG pillar, and overlying and contacting, said first polysilicon fill, comprised of a horizontal polysilicon shape, on said first polysilicon fill, and with vertical polysilicon shapes connected to said horizontal polysilicon shape, extending upwards from said horizontal polysilicon shape;

a second, multiple crown, polysilicon lower electrode, overlying said insulator shape, and overlying said third BPSG pillar, and said fourth BPSG pillar, and overlying and contacting, said third polysilicon fill, comprised of a horizontal polysilicon shape, on said third polysilicon fill, and with vertical polysilicon shapes connected to said horizontal polysilicon shape, extending upwards from said horizontal polysilicon shape;

a capacitor dielectric layer on said first, multiple crown, polysilicon lower electrode, and on said second, multiple crown, polysilicon lower electrode; and

an upper polysilicon electrode, on the capacitor dielectric layer that overlays said first, multiple crown, polysilicon lower electrode, and an upper polysilicon electrode, on the capacitor dielectric layer that overlays said second, multiple crown, polysilicon lower electrode.

2. The stacked capacitor structure, DRAM device, of claim 1, wherein said first, multiple crown, polysilicon lower electrode, and said second, multiple crown shaped, polysilicon lower electrode, are comprised of between about one to three, vertical polysilicon shapes, on each end of the multiple crown, polysilicon lower electrode, with each vertical polysilicon shape between about 3000 to 9000 Angstroms in height, and each between about 500 to 1500 Angstroms in width, and with said vertical polysilicon shapes connected to an underlying horizontal polysilicon shape, between about 1000 to 2000 Angstroms in thickness.

3. The stacked capacitor structure of claim 1, wherein spaces between said vertical polysilicon shapes, of said multiple crown shaped, polysilicon lower electrodes, is between about 300 to 1000 Angstroms.