Electrostatic discharge protection in integrated circuits, systems and methods

• US 5,804,861 A
• Filed: 10/21/1996
• Issued: 09/08/1998
• Est. Priority Date: 03/28/1991
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Leach, Jerald G.
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): GUAY, JOHN FRANCIS
• Application Number:
  US08/734,708
• Time in Patent Office: 687 Days
• Field of Search: 357/355, 357/356, 357/357, 357/362, 357/546, 357/378, 357/566, 357/567, 357/568, 361/91, 361/111, 361/56
• US Class Current: 257/362
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/011 Bipolar transistors

Abstract

An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Claims

1. An integrated circuit comprising:

a semiconductive substrate having an impurity concentration of a first type;

a first set of supply pins connected for a first supply voltage level and a second set of supply pins connected to said semiconductive substrate for a second supply voltage level;

said integrated circuit having internal circuits connected to said first and said second set of supply pins;

an electrostatic discharge protection circuit connected between at least two of said supply pins in said first set of supply pins, wherein said electrostatic discharge protection circuit includes a bipolar transistor, said semiconductive substrate acting as a collector for said bipolar transistor, said bipolar transistor having a base connected to a first of said supply pins in said first set of supply pins and an emitter connected to a second of said supply pins in said first set of supply pins.

2. The integrated circuit of claim 1 further comprising a signal pin and a CMOS buffer circuit connected to a pin in said first set, to a pin in said second set and to said signal pin.

3. An integrated circuit comprising:

a semiconductive substrate having an impurity concentration of a first type;

a first pin connected to said semiconductive substrate;

a first internal circuit connected to a second pin;

a second internal circuit connected to said semiconductive substrate, said second internal circuit also connected to a third pin, said second internal circuit operable to conduct a current from said third pin to said first pin in response to a voltage applied to said third pin; and

an electrostatic discharge protection circuit connected between said second pin and said third pin, wherein said electrostatic discharge protection circuit includes a bipolar transistor, said semiconductive substrate forming a collector for said bipolar transistor, said bipolar transistor having an emitter connected to said second pin and a base connected to said third pin, said bipolar transistor operable to conduct a first portion of an electrostatic discharge current through said base to said second internal circuit in response to an electrostatic discharge voltage applied to said second pin;

said bipolar transistor further operable to conduct an amplified portion of said first portion of said electrostatic discharge current into said semiconductive substrate, whereby said electrostatic discharge voltage is dissipated in said semiconductive substrate and said first internal circuit and said second internal circuit are protected from damage from said electrostatic discharge voltage.

4. The integrated circuit of claim 3, wherein said bipolar transistor further comprises:

an N-tank formed in said semiconductive substrate, said n-tank having an impurity concentration of a second type opposite to said first type, wherein said n-tank forms said base;

a first contact region having an impurity concentration of said second type formed within a boundary of said n-tank, said first contact region being in contact with said third pin; and

a second contact region having an impurity concentration of said first type formed within the boundary of said n-tank, said second contact region being in contact with said second pin and forming said emitter.

5. The integrated circuit of claim 4, further comprising a guard ring having an impurity concentration of said first type formed in a band surrounding and separated from said n-tank, said guard ring being in contact with said first pin.

6. The integrated circuit of claim 4, wherein said first contact region is formed in a band surrounding and separated from said second contact region.

7. The integrated circuit of claim 4 wherein said first pin is operable to provide a ground voltage to said first and second internal circuits, said second pin is operable to provide a first positive supply voltage to said first internal circuit, and said third pin is operable to provide a second positive supply voltage to said second internal circuit.

8. The integrated circuit of claim 4, wherein said first pin is operable to provide a first ground supply voltage to said second internal circuit, said second pin is operable to provide a second ground supply voltage to said first internal circuit, and said third pin is operable to provide a positive supply voltage to said second internal circuit.

9. The integrated circuit of claim 4, wherein said first pin is operable to provide a ground voltage to said first and second internal circuits, said second pin is operable to provide an output signal from said first internal circuit, and said third pin is operable to provide a positive supply voltage to said second internal circuit.

10. An electronic system comprising:

a printed circuit board and at least one integrated circuit thereon;

wherein said printed circuit board further comprises at least first and second conductors thereon, said first conductor connected to carry a supply voltage of a first level to said integrated circuit having a first set of supply pins connected to said first conductor and a second set of supply pins connected to said second conductor, and said integrated circuit having internal circuits connected to said first and second sets of supply pins;

wherein said integrated circuit further comprises;

a semiconductive substrate having an impurity concentration of a first type;

a first pin of said first set of supply pins connected to said semiconductive substrate;

a first internal circuit connected to a second pin;

a second internal circuit connected to said semiconductive substrate, said second internal circuit also connected to a third pin of said second set of supply pins, said second internal circuit operable to conduct a current from said third pin to said first pin in response to a voltage applied to said third pin; and

an electrostatic discharge protection circuit connected between said second pin and said third pin, wherein said electrostatic discharge protection circuit includes a bipolar transistor, said semiconductive substrate forming a collector for said bipolar transistor, said bipolar transistor having an emitter connected to said second pin and a base connected to said third pin, said bipolar transistor operable to conduct a first portion of an electrostatic discharge current through said base to said second internal circuit in response to an electrostatic discharge voltage applied to said second pin;

said bipolar transistor further operable to conduct an amplified portion of said first portion of said electrostatic discharge current into said semiconductive substrate, whereby said electrostatic discharge voltage is dissipated in said semiconductive substrate and said first internal circuit and said second internal circuit are protected from damage from said electrostatic discharge voltage.

11. The integrated circuit of claim 10, wherein said bipolar transistor further comprises:

an N-tank formed in said semiconductive substrate, said n-tank having an impurity concentration of a second type opposite to said first type, wherein said n-tank forms said base;

a first contact region having an impurity concentration of said second type formed within a boundary of said n-tank, said first contact region being in contact with said third pin; and

a second contact region having an impurity concentration of said first type formed within the boundary of said n-tank, said second contact region being in contact with said second pin and forming said emitter.

12. The integrated circuit of claim 11, further comprising a guard ring having an impurity concentration of said first type formed in a band surrounding and separated from said n-tank, said guard ring being in contact with said first pin.

13. The integrated circuit of claim 11, wherein said first contact region is formed in a band surrounding and separated from said second contact region.

14. The integrated circuit of claim 11, wherein said first pin is operable to provide a ground voltage to said first and second internal circuits, said second pin is operable to provide a first positive supply voltage to said first internal circuit, and said third pin is operable to provide a second positive supply voltage to said second internal circuit.

15. The integrated circuit of claim 11, wherein said first pin is operable to provide a first ground supply voltage to said second internal circuit, said second pin is operable to provide a second ground supply voltage to said first internal circuit, and said third pin is operable to provide a positive supply voltage to said second internal circuit.

16. The integrated circuit of claim 11, wherein said first pin is operable to provide a ground voltage to said first and second internal circuits, said second pin is operable to provide an output signal from said first internal circuit, and said third pin is operable to provide a positive supply voltage to said second internal circuit.