Resonant bilateral charging and discharging circuit

• US 5,804,943 A
• Filed: 05/12/1995
• Issued: 09/08/1998
• Est. Priority Date: 05/12/1995
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kollman, Robert L., Sills, James G.
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): Law, Patrick B.
• Application Number:
  US08/439,933
• Time in Patent Office: 1,215 Days
• Field of Search: 320/1, 323/289, 323/290, 327/108, 327/109, 327/365, 327/390, 327/391
• US Class Current: 320/167
• CPC Class Codes: H02M 3/3384 of the parallel type
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A bilateral switch (302) plus inductance (304) to drive a capacitive load (306 plus 350) by resonant charging and discharging the load.

Claims

1. A charging and discharging circuit for a capacitive load, comprising:

(a) an inductance coupled to an output node;

(b) a bilateral switch coupling said inductance to a supply voltage; and

(c) a controller switching said bilateral switch, wherein said controller provides turn on and turn off pulses for said bilateral switch with pulse duration for both turn on and turn off pulses equal to about π

√

(LC) with L said inductance and C the capacitance at said output node.

2. The circuit of claim 1, further comprising:

(a) a pulldown switch coupling said output node to a reference voltage; and

(b) said controller switching said pulldown switch;

(c) whereby said controller provides turn on pulses for said pulldown switch after ones of said turn off pulses.

3. The circuit of claim 1, wherein:

(a) said capacitive load charges to at least 1.5 times said supply voltage.

4. The circuit of claim 1, further comprising:

(a) a capacitor in parallel with said pulldown switch.

5. The circuit of claim 4, wherein:

(a) said bilateral switch is a vertical field effect transistor;

(b) said pulldown switch is a field effect transistor; and

(c) said reference potential is ground.

6. The circuit of claim 5, wherein:

(a) said vertical field effect transistor is made of GaAs.

7. A method of charging and discharging a capacitive load, comprising the steps of:

(a) connecting a discharged capacitive load to a voltage supply through an inductance to charge said capacitive load;

(b) disconnecting said capacitive load from said voltage supply after a time interval of about π

√

(LC) with L said inductance and C the capacitance at said load;

(c) connecting said charged capacitive load to a voltage supply through said inductance; and

(d) disconnecting said capacitive load from said voltage supply after a time interval of about π

√

(LC).

8. The method of claim 7, wherein:

(a) said connecting and disconnecting is by a vertical field effect transistor turning on and off.

9. The method of claim 8, further comprising the steps of:

(a) after a second time interval, again connecting said capacitive load to said voltage supply through said inductance; and

(b) again disconnecting said capacitive load from said voltage supply after a time interval of about π

√

(LC).

10. The method of claim 9, wherein:

(a) said capacitive load charges to at least 1.5 times said voltage supply.