Input current modulation for power factor correction

• US 5,804,950 A
• Filed: 06/20/1996
• Issued: 09/08/1998
• Est. Priority Date: 06/20/1996
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Micro Linear Corporation (Qorvo, Inc.)
• Inventors: Ki, Wing-Hung, Hwang, Jeffrey H.
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): PATEL, RAJNIKANT B
• Application Number:
  US08/667,117
• Time in Patent Office: 810 Days
• Field of Search: 323/207, 323/222, 323/284, 323/282, 323/275, 323/286, 363/21, 363/59, 363/89, 363/17
• US Class Current: 323/222
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

A nonlinear carrier controlled power factor correction circuit operates in the continuous and discontinuous conduction modes and provides unity power factor at the input of a power supply by only sensing the output voltage and the current flowing through a diode of a rectifier circuit. The power factor correction circuit monitors a level of current flowing through the diode and generates an integrated voltage signal representative of the level of current flowing through the diode. The integrated voltage signal is compared to a periodic, carrier waveform signal generated using a feedback signal corresponding to a level of an output voltage delivered to a load. A difference between the feedback signal and a reference signal determines the waveshape and characteristics of the carrier waveform. Preferably, leading edge modulation is used to control the duty cycle of a switch within the rectifier circuit. The switch is turned on when the integrated voltage signal reaches a level greater than the value of the carrier waveform. The switch is turned off at the leading edge of the clock reference signal. The duty cycle of the switch will vary as the level of the output voltage varies in reference to the reference signal and as the level of current through the diode varies.

Claims

1. A power factor correction circuit using input current modulation for controlling a switch in a rectifier circuit, wherein the rectifier circuit includes the switch and a diode and is configured for coupling to a load, comprising:

a. first means for generating an integrated signal representative of a level of current flowing through the diode configured for receiving a signal representative of the level of current flowing through the diode;

b. second means for generating a carrier waveform signal representative of a difference between a level of voltage supplied to the load and a reference voltage configured for coupling to the load;

c. means for comparing the integrated signal to the carrier waveform signal and generating an output signal coupled to receive the integrated signal and the carrier waveform signal for generating an output signal in response to a comparison; and

d. means for controlling coupled to the means for comparing and configured for coupling to the switch for controlling the operation of the switch in response to the output signal.

2. The power factor correction circuit as claimed in claim 1 further comprising an oscillating circuit coupled to the means for controlling for generating a clock reference signal.

3. The power factor correction circuit as claimed in claim 2 wherein leading edge modulation is used by the means for controlling to control the switch.

4. The power factor correction circuit as claimed in claim 3 wherein the means for controlling closes the switch when the integrated signal is greater than the carrier waveform signal and opens the switch at a leading edge of the clock reference signal.

5. The power factor correction circuit as claimed in claim 4 further comprising current sensing means coupled to the rectifier circuit and to the first means for generating for measuring the level of current flowing through the diode.

6. The power factor correction circuit as claimed in claim 5 wherein the current sensing means includes a sense resistor.

7. The power factor correction circuit as claimed in claim 6 wherein the first means for generating includes an integrating circuit with a reset switch.

8. The power factor correction circuit as claimed in claim 7 wherein the second means for generating includes an error amplifier.

9. The power factor correction circuit as claimed in claim 8 wherein the rectifier circuit is a boost configuration.

10. The power factor correction circuit as claimed in claim 8 wherein the rectifier circuit is a buck configuration.

11. The power factor correction circuit as claimed in claim 8 wherein the rectifier circuit is a flyback configuration.

12. A power factor correction circuit using input current modulation for controlling a switch in a rectifier circuit, wherein the rectifier circuit includes the switch and a diode and is configured for coupling to a load, comprising:

a. means for monitoring a level of current flowing through the diode;

b. first means for generating coupled to the means for monitoring for generating an integrated signal representative of the level of current flowing through the diode;

c. second means for generating configured for coupling to the load for generating a carrier waveform signal representative of a difference between a level of voltage supplied to the load and a reference voltage;

d. means for comparing coupled to the first and second means for generating for comparing the integrated signal to the carrier waveform signal and generating an output signal; and

e. means for controlling the switch configured for coupling to the switch and coupled to the means for comparing for controlling operation of the switch in response to the output signal.

13. The power factor correction circuit as claimed in claim 12 further comprising an oscillating circuit coupled to the means for controlling for generating a clock reference signal of a predetermined period having a leading edge and a trailing edge.

14. The power factor correction circuit as claimed in claim 13 wherein leading edge modulation is used by the means for controlling to control the switch.

15. The power factor correction circuit as claimed in claim 14 wherein the means for controlling closes the switch when a value of the integrated signal is greater than a value of the carrier waveform signal and opens the switch on the leading edge of the clock reference signal.

16. The power factor correction circuit as claimed in claim 15 wherein the means for monitoring includes a sense resistor.

17. A method of controlling a switch in a rectifier circuit, wherein the rectifier circuit includes the switch and a diode and is configured for coupling to a load, comprising the steps of:

a. generating an integrated signal representative of a level of current flowing through the diode;

b. generating a carrier waveform signal representative of a difference between a level of voltage supplied to the load and a reference voltage;

c. generating an output signal representative of relative levels of the integrated signal and the carrier waveform signal, wherein the output signal is at a logical low voltage level when a value of the integrated signal is less than a value of the carrier waveform and the output signal is at a logical high voltage level when the value of the integrated signal is greater than the value of the carrier waveform; and

d. generating a control signal for controlling the switch wherein the control signal turns the switch on when the output signal is at a logical high voltage level.

18. The method as claimed in claim 17 further comprising the step of generating a clock reference signal.

19. The method as claimed in claim 18 wherein the control signal turns the switch off when the clock reference signal rises to a logical high voltage level.

20. A rectifier and power factor correction circuit for supplying power to a load from an input voltage source comprising:

a. a storage device for storing voltage drawn from the input source and supplying a supplied amount of voltage to a load device;

b. a switching circuit coupled between the storage device and the input source, having an on configuration and an off configuration, wherein voltage is only drawn from the input source when the switching circuit is in the on configuration;

c. a diode coupled between the storage device and the switching circuit;

d. a monitoring circuit coupled to the diode for monitoring a level of current through the diode;

e. an integrating circuit coupled to the monitoring circuit for generating an integrated signal representative of the level of current flowing through the diode;

f. a generating circuit configured for coupling to the load for generating a carrier waveform signal representative of a difference between a level of voltage supplied to the load and a reference voltage;

g. a comparing circuit coupled to the integrating circuit and to the generating circuit for comparing the integrated signal to the carrier waveform signal and generating a control signal; and

h. a controlling circuit coupled to the switching circuit and to the comparing circuit for controlling operation of the switching circuit in response to the control signal.

21. The power factor correction circuit as claimed in claim 20 further comprising an oscillating circuit coupled to the means for controlling for generating a clock reference signal of a predetermined period having a leading edge and a trailing edge.

22. The power factor correction circuit as claimed in claim 21 wherein the control signal is at a logical low voltage level when a value of the integrated signal is less than a value of the carrier waveform signal and at a logical high voltage level when the value of the integrated signal is greater than the value of the carrier waveform signal.

23. The power factor correction circuit as claimed in claim 22 wherein the controlling circuit closes the switch when the control signal is at a logical high voltage level and opens the switch on the leading edge of the clock reference signal.

24. A power factor correction circuit comprising:

a. means for sensing an input current for forming a current sense signal;

b. first means for integrating the current sense signal over a period of a clock signal for forming a first integrated signal, the first means for integrating coupled to the means for sensing;

c. first means for comparing an output voltage to a desired output voltage for forming an error signal;

d. second means for integrating the error signal over the period of the clock signal for forming a second integrated signal, the second means for integrating coupled to the first means for comparing;

e. means for squaring the second integrated signal for forming a squared signal, the means for squaring coupled to second means for integrating; and

f. second means for comparing the squared signal to the first integrated signal for forming a control signal; and

g. means for modulating the input current coupled to receive the control signal.

25. The power factor correction circuit according to claim 24 wherein the clock signal is periodic and each period has a leading edge and a trailing edge and wherein the means for modulating modulates the input current according to the leading edge.

26. The power factor correction circuit according to claim 25 wherein the means for modulating closes a switch through which the input current flows when a value of the integrated signal is greater than a value of the squared signal and opens the switch upon the leading edge.