Circuits for testing the function circuit modules in an integrated circuit

• US 5,804,960 A
• Filed: 09/27/1996
• Issued: 09/08/1998
• Est. Priority Date: 01/28/1991
• Status: Expired due to Fees

• Current Assignee: Actel Corporation (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: El Ayat, Khaled, Speers, Theodore M., Chan, King W.
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US08/722,355
• Time in Patent Office: 711 Days
• Field of Search: 324/73.1, 324/158.1, 324/765, 324/763, 371/22.1, 371/22.2, 371/22.3, 371/22.6, 371/23, 326/16, 326/39, 326/40, 364/483, 364/550.01
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]

Abstract

A circuit for providing 100% observability and controllability of inputs and outputs of any function circuit module in an array of function circuit modules includes circuitry for placing a test data bit into a selected one of any of the function circuit modules, and circuitry for reading the output of a selected one of any of the function circuit modules.

Claims

1. In an integrated circuit including a plurality of function circuit modules, each of said function circuit modules having inputs and at least one output, each of said function circuit modules being programmable to perform a defined function selectable from among a plurality of potential functions, said integrated circuit further including:

control means contained within each of said function circuit modules, responsive to first addressing signals, for directly forcing the output of said function circuit module to assume a selected logic state said control means being independent of the defined function of said function circuit module and interconnection between said function circuit module and other ones of said function circuit modules; and

observe means contained within said integrated circuit, responsive to second addressing signals, for observing the output of any selected one of said function circuit modules at a single I/O pin of said integrated circuit;

said control means and said observe means being simultaneously operable.

2. In an integrated circuit having a plurality of function circuit modules each having inputs and at least one output, each of said function circuit modules being programmable to perform a defined function selectable from among a plurality of potential functions, a circuit for providing 100% controllability and observability of said outputs of each of said function circuit modules including:

select means for selecting any one of said function circuit modules;

control means associated with each of said function circuit modules and responsive to said select means, for directly forcing the output of any of said function circuit modules to assume a selected logic state, said control means being independent of the defined function of and interconnection between said function circuit modules; and

observe means associated with each of said function circuit modules and responsive to said select means, for directly reading the output of any of said function circuit modules at a single I/O pin of said integrated circuit.

3. In an integrated circuit including a plurality of function circuit modules having inputs and at least one output, each of said function circuit modules being programmable to perform a defined function selectable from among a plurality of potential functions, a circuit for providing 100% controllability of said outputs of each of said function circuit modules including:

a test data input node in each of said function circuit modules in said integrated circuit;

addressing means for selecting any one of said function circuit modules;

test data path means, directly communicating between an input/output pin of said integrated circuit and each of said test data input nodes of said function circuit modules, for providing a user-selectable logic level present at said input/output pin directly to said test data input nodes of each of said function circuit modules; and

control means for forcing the output of the one of said function modules selected by said addressing means to assume a logic state related to said test data, said control means being independent of the defined function of and interconnection between said function circuit modules.

4. In an integrated circuit including a plurality of function circuit modules having inputs and at least one output, each of said function circuit modules being programmable to perform a defined function selectable from among a plurality of potential functions, a circuit for providing 100% controllability and 100% observability of said outputs of each of said function circuit modules including:

a test data input node in each of said function circuit modules contained in said integrated circuit;

addressing means for selecting any one of said function circuit modules;

test data path means, communicating between an input/output pin of said integrated circuit and said test data input nodes of each of said function circuit modules, for providing a user-selectable logic level present at said input/output pin directly to said test data input nodes of each of said function circuit modules;

control means for directly forcing the output of the one of said function modules selected by said addressing means to assume a logic state related to said test data, said control means being independent of the defined function of and interconnection between said function circuit modules; and

observe means for reading an output state of the one of said function circuit modules selected by said addressing means directly to an input/output pin of said integrated circuit.

5. In an integrated circuit including a plurality of function circuit modules, each of said function circuit modules having inputs and at least one output, each of said function circuit modules being programmable to perform a defined function selectable from among a plurality of potential functions, a circuit for providing 100% controllability of the outputs of each of said function circuit modules including:

isolation means associated with each of said function circuit modules for isolating its output from its inputs; and

latching means for latching a user-selectable logic level at the output of each of said function circuit modules.

6. An integrated circuit including:

an array of identical logic function circuits which may be mask programmed to perform any one of a plurality of combinational and sequential logic functions, each of said logic function circuits having inputs and at least one output, said integrated circuit configured to mask programmably connect said logic function circuits to each other in a random fashion;

isolation means within each one of said logic function circuits for isolating its output from its inputs;

test data input node in each of said logic function circuits;

latching means disposed in each of said logic function circuits and coupled to said test data input node, for latching a selected logic state from said test data input node at the output of each of said logic function circuits; and

observe means for reading the output of any one of said logic function circuits directly to an input/output pin of said integrated circuit;

whereby each of said logic function circuits may be individually and directly controlled and observed.

7. An integrated circuit including:

an array of identical logic function circuits which may be mask programmed to perform any one of a plurality of combinatorial and sequential logic functions, each of said logic function circuits having inputs and at least one output, said integrated circuit configured to mask programmably connect said logic function circuits to each other in a random fashion;

logic state input means, directly coupled between an input/output pin on said integrated circuit and a test data input node in each of said logic function circuits, for selectively presenting a user-selectable logic state to each one of said logic function circuits;

latching means in each one of said logic function circuits, coupled to said test data input nodes thereof and responsive to a latching signal, for latching said user-selectable logic state into its logic function circuit; and

selection means, coupled to each of said logic function circuits and responsive to signals from off of said integrated circuit, for providing said latching signal to any one of said logic function circuits;

whereby each of said logic function circuits may be individually and directly controlled.