Time-division data multiplexer with feedback for clock cross-over adjustment

• US 5,805,089 A
• Filed: 10/21/1996
• Issued: 09/08/1998
• Est. Priority Date: 09/05/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Krishnan, Shoba, Fiedler, Alan S.
• Primary Examiner(s): Young, Brian K.
• Application Number:
  US08/734,691
• Time in Patent Office: 687 Days
• Field of Search: 341/101, 341/100, 340/870.13
• US Class Current: 341/101
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00

Abstract

A time-division data multiplexer has feedback for adjusting the select clock cross-over voltage. The multiplexer includes a multi-phase clock generator having a plurality of select clock outputs with different phases, a plurality of parallel data inputs and first and second serial data outputs. A first set of gating transistors is coupled between the first data output and a common node. Each transistor in the first set is gated by a corresponding data input and at least one corresponding select clock output. A second set of gating transistors is coupled between the second data output and the common node. Each transistor in the second set is gated by a corresponding data input and at least one corresponding select clock output. A first current source is coupled to the common node. An amplifier has a first input which is coupled to the common node, a second input which is coupled to a reference voltage generator and a cross-over control output which is coupled to the plurality of select clock outputs for adjusting the cross-over voltage of the select clock outputs in response to a comparison of the voltages on the first and second amplifier inputs. A loop filter is coupled to the cross-over control output.

Claims

1. A time-division multiplexer with an adjustable clock cross-over voltage, comprising:

a multi-phase clock generator comprising a plurality of select clock outputs with different phases;

a plurality of data inputs;

first and second data outputs;

a first set of gating transistors which is coupled between the first data output and a common node, with each transistor in the first set being gated by a corresponding data input and at least one corresponding select clock output;

a second set of gating transistors which is coupled between the second data output and the common node, with each transistor in the second set being gated by a corresponding data input and at least one corresponding select clock output;

a first current source coupled to the common node;

a reference voltage generator; and

an amplifier comprising a first input coupled to the common node, a second input coupled to the reference voltage generator and a cross-over control output coupled to the plurality of select clock outputs for adjusting cross-over of the select clock outputs.

2. The time-division multiplexer of claim 1 wherein the reference voltage generator comprises:

a reference transistor and a second current source coupled together in series and defining a reference node between the reference transistor and the second current source; and

wherein the reference node is coupled to the second input of the amplifier.

3. The time-division multiplexer of claim 2 wherein the reference transistor has a continuously enabled state.

4. The time-division multiplexer of claim 2 and further comprising:

first and second supply terminals;

a first load resistor coupled between the first data output and the first supply terminal;

a second load resistor coupled between the second data output and the first supply terminal;

a third load resistor coupled between the reference transistor and the first supply terminal;

wherein the first current source is coupled between the common node and the second supply terminal; and

wherein the second current source is coupled between the reference node and the second supply terminal.

5. The time-division multiplexer of claim 4 wherein:

the first, second and third load resistors have equal resistances;

the first and second sets of transistors and the reference transistor have equal gate widths and lengths; and

the first and second current sources supply equal currents.

6. The time-division multiplexer of claim 4 wherein:

the first and second load resistors have a resistance R;

the first and second sets of transistors have a gate width W;

the first current source supplies a tail current I_MUX to the common node;

the third load resistor has a resistance R*N;

the reference transistor has a gate width W/N;

the reference transistor and the first and second sets of transistors have a gate length L;

the second current source supplies a tail current I_MUX /N to the reference node; and

N is a selected variable.

7. The time-division multiplexer of claim 1 wherein the multi-phase clock generator comprises:

a voltage-controlled oscillator comprising a plurality of differential, voltage-controlled delay elements coupled together in a ring, wherein each delay element has a differential input coupled to a differential output of another delay element in the ring; and

a differential-to-CMOS level buffer having a differential input coupled to the differential output of a corresponding delay element and having first and second complementary logic outputs which drive respective select clock outputs.

8. The time-division multiplexer of claim 7 and further comprising:

a first, relatively positive supply terminal and a second, relatively negative supply terminal;

a first N-channel cross-over adjustment transistor coupled between the first output of the differential-to-CMOS level buffer and the second supply terminal and having a control terminal coupled to the cross-over control output; and

a second N-channel cross-over adjustment transistor coupled between the second output of the differential-to-CMOS level buffer and the second supply terminal and having a control terminal coupled to the cross-over control output.

9. The time-division multiplexer of claim 8 wherein the differential-to-CMOS level buffer further comprises first and second inverters coupled between the first and second complementary logic outputs, respectively, and the respective select clock outputs.

10. The time-division multiplexer of claim 9 wherein the amplifier comprises a differential amplifier having an inverting input coupled to the common node and a non-inverting input coupled to the reference voltage generator.

11. The time-division multiplexer of claim 9 wherein the differential-to-CMOS level buffer comprises a plurality of transistors which have gate widths that are sized such that the respective select clock outputs cross over one another at a voltage which is lower than an optimum voltage.

12. The time-division multiplexer of claim 7 and further comprising:

a first, relatively positive supply terminal and a second, relatively negative supply terminal;

a first P-channel cross-over adjustment transistor coupled between the first output of the differential-to-CMOS level buffer and the first supply terminal and having a control terminal coupled to the cross-over control output; and

a second P-channel cross-over adjustment transistor coupled between the second output of the differential-to-CMOS level buffer and the first supply terminal and having a control terminal coupled to the cross-over control output.

13. The time-division multiplexer of claim 12 wherein the differential-to-CMOS level buffer further comprises first and second inverters coupled between the first and second complementary logic outputs, respectively, and the respective select clock outputs and comprises a plurality of transistors which have gate widths that are sized such that the respective select clock outputs cross over one another at a voltage which is higher than an optimum voltage.

14. The time-division multiplexer of claim 13 wherein the amplifier comprises a differential amplifier having a non-inverting input coupled to the common node and an inverting input coupled to the reference voltage generator.

15. The time-division multiplexer of claim 1 and further comprising a loop filter coupled to the cross-over control output.

16. An n:

1 time-division multiplexer, where n is an even integer, the multiplexer comprising;

clock generator means for generating n/2 pairs of select clock signals, wherein the select clock signals in each pair are approximately 180 degrees out of phase with one another and have an adjustable cross-over voltage, and wherein the n select clock signals are equally distributed in phase over 360 degrees;

a set of n true and complement data inputs;

first and second data outputs;

a first set of n gating transistors coupled between the first data output and a common node, with each transistor in the first set being gated by a corresponding true data input and corresponding select clock signals;

a second set of n gating transistors coupled between the second data output and the common node, with each transistor in the second set being gated by a corresponding complement data input and the corresponding select clock signals;

first current source means for supplying a tail current to the common node;

reference means for generating a reference voltage on a reference node which is representative of a voltage on the common node when only one of the transistors in the n pairs of data gating transistors is enabled at one time;

means for comparing the voltages on the reference node and the common node and for generating a cross-over control output which is representative of the comparison; and

means for adjusting the cross-over voltage of the select clock outputs as a function of the cross-over control output.

17. A time-division multiplexer comprising:

first and second supply terminals;

a multi-phase clock generator comprising a plurality of select clock outputs with different phases;

a set of true and complement data inputs;

first and second data outputs;

a first set of gating transistors coupled between the first data output and a common node, with each transistor in the first set being gated by a corresponding true data input and at least one corresponding select clock output;

a second set of gating transistors coupled between the second data output and the common node, with each transistor in the second set being gated by a corresponding complement data input and at least one corresponding select clock output;

reference means for generating a reference voltage which is representative of an average of the voltages on the first and second data outputs when only one of the transistors in the first and second sets is enabled;

means for comparing the average of the voltages on the first and second data outputs with the reference voltage and for generating a cross-over control output which is representative of the comparison; and

means for adjusting the cross-over voltage of the select clock outputs as a function of the cross-over control output.

18. The time-division multiplexer of claim 17 and further comprising:

first and second termination resistors coupled between the first supply terminal and the first and second data outputs, respectively;

first and second measurement resistors coupled in series between the first and second data outputs;

wherein the reference means comprises third and fourth termination resistors and a reference transistor coupled together in series between the first and second supply terminals;

wherein the comparison means comprises a differential amplifier having a non-inverting input coupled to a node between the first and second measurement resistors, an inverting input coupled to a node between the third and fourth termination resistors, and an output which forms the cross-over control output; and

wherein the means for adjusting the cross-over voltage comprises a transistor coupled between each select clock output and the second supply terminal and having a control terminal coupled to the cross-over control output.

19. The time-division multiplexer of claim 18 wherein the first and second termination resistors each have a resistance R and the third and fourth termination resistors each have a resistance R/2.

20. A method of serializing a plurality of parallel data inputs to a pair of data outputs, comprising:

generating at least one pair of select clock signals which are approximately 180 degrees out of phase with one another;

selectively coupling the data outputs to a common node as a function of the plurality of data inputs and the select clock signals;

comparing the voltage on the common node with a reference voltage; and

adjusting cross-over of the select clock signals as a function of the comparison.