Apparatus and method for processing multiple frequencies in satellite navigation systems

• US 5,805,108 A
• Filed: 09/16/1996
• Issued: 09/08/1998
• Est. Priority Date: 09/16/1996
• Status: Expired due to Term

• Current Assignee: Trimble Navigation Limited (Trimble Inc.)
• Original Assignee: Trimble Navigation Limited (Trimble Inc.)
• Inventors: Lennen, Gary R.
• Primary Examiner(s): Tarcza, Thomas H.
• Assistant Examiner(s): Phan, Dao L.
• Application Number:
  US08/714,188
• Time in Patent Office: 722 Days
• Field of Search: 342/352, 342/357, 364/449.7, 364/449.1, 375/200
• US Class Current: 342/357.68
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/32 Multimode operation in a single same satellite system, e.g. GPS L1/L2
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain

Abstract

The multiple frequency satellite correlation receiver is disclosed. The three frequency receiver allows one to significantly enhance the widelane carrier phase measurements in order to improve the differential and survey navigation applications.

Claims

1. A system for optimum correlation processing of at least three signals M1, M2, and M3 emanating from the same satellite belonging to the satellite positioning system (SPS), said system comprising:

a RECEIVING CIRCUIT for receiving and preparing for processing each said M1, M2, and M3 signal; and

a DIGITAL SIGNAL PROCESSING CIRCUIT for processing each said M1, M2, and M3 signal in order to perform the code and carrier measurements to solve for user'"'"'s position, velocity, and time coordinate;

wherein the availability of at least three M1, M2, and M3 signals increases the accuracy in finding the user'"'"'s position, velocity, and time coordinate.

2. A system for optimum correlation processing of at least three L1, L2, and L3 signals received from a SPS satellite by a SPS RECEIVER, said system comprising:

a RECEIVING CIRCUIT for receiving a known C/A code and a known P(Y) code modulated on L1 carrier frequency signal, for receiving a known P(Y) code modulated on L2 carrier frequency signal, and for receiving a known C/A code modulated on L3 carrier frequency from at least one satellite;

wherein said received L1, L2, and L3 signals contain propagation noise; and

at least one DIGITAL CHANNEL PROCESSING CIRCUIT for;

(1) locally generating replica of said C/A code modulated on L1 carrier frequency signal and on L3 carrier frequency;

(2) locally generating replica of said P(Y) code modulated on L1 carrier frequency signal and on L2 carrier frequency signal;

(3) correlating a locally generated replica of C/A or P(Y) code with the received L1 code for obtaining an estimate of L1 group delay (L1 pseudo-range) and L1 carrier phase;

(4) correlating a locally generated replica of P(Y) code with the received L2 code for obtaining an estimate of L2 group delay (L2 pseudo-range) and L2 carrier phase; and

(5) correlating a locally generated replica of C/A code with the received L3 code for obtaining an estimate of L3 group delay (L3 pseudo-range) and L3 carrier phase.

3. The system of claim 2, wherein said RECEIVING CIRCUIT further comprises:

a triple frequency patch ANTENNA CIRCUIT for receiving said L1, L2, and L3 satellite signals;

a FILTER /LNA CIRCUIT conductively connected to said ANTENNA CIRCUIT for performing filtering and low noise amplification of said L1, L2, and L3 signals, wherein said FILTER/LNA determines the signal/noise ratio of the received signals L1, L2, and L3;

a DOWNCONVERTER CIRCUIT conductively connected to said FILTER/LNA CIRCUIT for mixing and converting said L1, L2, and L3 signals; and

an IF PROCESSOR CIRCUIT conductively connected to said DOWNCONVERTER CIRCUIT for transforming said converted L1, L2, and L3 signals into digitally sampled quadrature versions of L1, L2, and L3 signals (IL1, QL1, IL2, QL2, IL3, QL3).

4. The system of claim 3 further comprising a MASTER OSCILLATOR CIRCUIT and a FREQUENCY SYNTHESIZER CIRCUIT conductively connected to said MASTER OSCILLATOR CIRCUIT, to said IF PROCESSOR CIRCUIT, to said DOWNCONVERTER CIRCUIT, and to at least one said DIGITAL CHANNEL PROCESSING CIRCUIT, wherein said FREQUENCY SYNTHESIZER CIRCUIT generates several timing signals.

5. The system of claim 3, wherein said FILTER /LNA CIRCUIT further comprises:

a POWERSPL1TTER CIRCUIT connected to said ANTENNA CIRCUIT for power splitting a single L1/L2/L3 signal received by said ANTENNA CIRCUIT into three separate L1, L2, and L3 signals;

three separate BANDPASS FILTER CIRCUIT connected to said POWERSPL1TTER CIRCUIT for filtering said L1, L2, and L3 signals independently; and

a POWER COMBINER CIRCUIT connected to each said BANDPASS FILTER CIRCUIT for power combining said L1, L2, and L3 signals into one combined signal L1/L2/L3 before feeding said combined L1/L2/L3 signal into said LNA CIRCUIT;

wherein said LNA outputs amplified and filtered combined Ll/L2/L3 signal.

6. The system of claim 4, wherein said FREQUENCY SYNTHESIZER CIRCUIT further comprises:

a first DIVIDER CIRCUIT connected to said MASTER OSCILLATOR CIRCUIT to divide said MASTER OSCILLATOR output signal to obtain an input signal;

a PHASE DETECTOR CIRCUIT for comparing phases of two signals, said first signal being said input signal, said second signal being a local reference signal, wherein minimum voltage output signal from said PHASE DETECTOR CIRCUIT represents maximum phase alignment of said two signals;

a LOOP FILTER CIRCUIT connected to said PHASE DETECTOR CIRCUIT for filtering out high frequency voltage noise, wherein an output LOOP FILTER CIRCUIT voltage signal includes a low frequency voltage noise;

a VOLTAGE CONTROLLED OSCILLATOR (VCO) CIRCUIT connected to said LOOP FILTER CIRCUIT, wherein a voltage signal at the input of said VCO causes frequency change in said VCO output signal, and wherein said VCO nominal output signal is locked to said reference signal; and

wherein said VCO nominal output signal is used as 1st local oscillator (LO1) signal;

a second DIVIDER CIRCUIT connected to said VCO to divide said VCO output signal to obtain 2nd local oscillator (LO2) signal;

a third DIVIDER CIRCUIT connected to said second DIVIDER CIRCUIT to divide said 2nd LO2 signal to obtain sampling clock (SCLK) signal;

a fourth DIVIDER CIRCUIT connected to said third DIVIDER CIRCUIT to divide said 2nd LO2 signal to obtain a signal MSEC, wherein said signal MSEC is used for measurement of local reference time;

a MULTIPL1ER CIRCUIT connected to said MASTER OSCILLATOR CIRCUIT for multiplying the MASTER OSCILLATOR output signal to obtain a 4th local oscillator clock signal LO4; and

a fifth DIVIDER CIRCUIT connected to said fourth DIVIDER CIRCUIT to divide said SCLK signal to obtain a reference signal, wherein said reference signal is used by said PHASE DETECTOR CIRCUIT.

7. The system of claim 4, wherein said FREQUENCY SYNTHESIZER CIRCUIT further comprises:

a "Divide by 5" block;

a PHASE DETECTOR CIRCUIT connected to said block "Divide by 5" for comparing 5 MHz input signal from said MASTER OSCILLATOR CIRCUIT with 5 MHz signal from said "Divide by 5" block, wherein minimum voltage output signal from said PHASE DETECTOR CIRCUIT represents maximum phase alignment of two said 5 MHz signals;

a LOOP FILTER CIRCUIT connected to said PHASE DETECTOR CIRCUIT for filtering out high frequency voltage noise;

a VOLTAGE CONTROLLED OSCILLATOR (VCO) CIRCUIT connected to said LOOP FILTER CIRCUIT, wherein voltage signal at the input of said VCO causes frequency change in said VCO output signal, and wherein said VCO nominal output 1400 MHz signal is locked to said 5 MHz reference signal; and

wherein said 1400 MHz VCO output signal is used as a 1st local oscillator (LO1);

a "Divide by 8" block connected to said VCO to divide said 1400 MHz VCO output signal by 8 to obtain a 175 MHz signal used as a 2nd LO2;

a "Divide by 7" block connected to said "Divide by 8" block to divide said 175 MHz signal by 7 to obtain a 25 MHz signal used as a sampling clock (SCLK);

a "Divide by 25000" block connected to said "Divide by 7" block to divide said 25 MHz signal by 25000 to obtain a 1 KHz signal (MSEC), wherein said MSEC signal is used for measurement of local reference time; and

a "Multiply by 2" block connected to said MASTER OSCILLATOR block to obtain a 20 MHz signal used as a fourth clocking signal LO4.

8. The system of claim 3, wherein said DOWNCONVERTER CIRCUIT further comprises:

a POWERSPLITTER CIRCUIT connected to said FILTER /LNA CIRCUIT and to said FREQUENCY SYNTHESIZER for power splitting said FILTER/LNA CIRCUIT output L1/L2/L3 signal into three signals;

a first MULTIPLIER CIRCUIT connected to said POWERSPLITTER CIRCUIT for multiplying said L1 signal with said 1st LO1 signal, wherein a first mixed signal is produced;

a second MULTIPLIER CIRCUIT connected to said POWERSPLITTER CIRCUIT for multiplying said L2 signal with said 1st LO1 signal, wherein a second mixed signal is produced;

a third MULTIPLIER CIRCUIT connected to said POWERSPLITTER CIRCUIT for multiplying said L3 signal with said 1st LO1 signal, wherein a third mixed signal is produced;

a first BANDPASS FILTER CIRCUIT connected to said first MULTIPLIER CIRCUIT for filtering said first mixed signal;

a second BANDPASS FILTER CIRCUIT connected to said second MULTIPLIER CIRCUIT for filtering said second mixed signal;

a third BANDPASS FILTER CIRCUIT connected to said third MULTIPLIER CIRCUIT for filtering said third mixed signal;

a first AMPLIFIER CIRCUIT connected to said first BANDPASS FILTER CIRCUIT for amplifying said first filtered signal;

a second AMPLIFIER CIRCUIT connected to said second BANDPASS FILTER CIRCUIT for amplifying said second filtered signal; and

a third AMPLIFIER CIRCUIT connected to said third BANDPASS FILTER CIRCUIT for amplifying said third filtered signal.

9. The system of claim 3, wherein said IF PROCESSOR CIRCUIT further comprises:

a first POWERSPLITTER CIRCUIT connected to said DOWNCONVERTER CIRCUIT and to said FREQUENCY SYNTHESIZER CIRCUIT for power splitting said L1 signal into two signals;

a second POWERSPLITTER CIRCUIT connected to said DOWNCONVERTER CIRCUIT and to said FREQUENCY SYNTHESIZER CIRCUIT for power splitting said L2 signal into two signals;

a third POWERSPLITTER CIRCUIT connected to said DOWNCONVERTER CIRCUIT and to said FREQUENCY SYNTHESIZER CIRCUIT for power splitting said L3 signal into two signals;

a first MULTIPLIER CIRCUIT for multiplying said L1 signal with an inphase (I) version of said 2nd LO2 signal to produce an IL1 signal;

a second MULTIPLIER CIRCUIT for multiplying said L1 signal with a quadrature (Q) version of said 2nd LO2 signal to produce a QL1 signal;

a third MULTIPLIER CIRCUIT for multiplying said L2 signal with an inphase (I) version of said 2nd LO2 signal to produce an IL2 signal;

a fourth MULTIPLIER CIRCUIT for multiplying said L2 signal with a quadrature (Q) version of said 2nd LO2 signal to produce a QL2 signal;

a fifth MULTIPLIER CIRCUIT for multiplying said L3 signal with an inphase (I) version of said 4th LO4 signal to produce an IL3 signal;

a sixth MULTIPLIER CIRCUIT for multiplying said L3 signal with a quadrature (Q) version of said 4th LO4 signal to produce a QL3 signal;

a first AMPLIFIER CIRCUIT connected to said first MULTIPLIER CIRCUIT for amplifying said IL1 signal;

a second AMPLIFIER CIRCUIT connected to said second MULTIPLIER CIRCUIT for amplifying said QL1 signal;

a third AMPLIFIER CIRCUIT connected to said third MULTIPLIER CIRCUIT for amplifying said IL2 signal;

a fourth AMPLIFIER CIRCUIT connected to said fourth MULTIPLIER CIRCUIT for amplifying said QL2 signal;

a fifth AMPLIFIER CIRCUIT connected to said fifth MULTIPLIER CIRCUIT for amplifying said IL3 signal;

a sixth AMPLIFIER CIRCUIT connected to said sixth MULTIPLIER CIRCUIT for amplifying said QL3 signal;

a first one-bit analog-to-digital (A/D) CONVERTER CIRCUIT connected to said first AMPLIFIER CIRCUIT for performing 1-bit quantization operation on said IL1 signal;

a second one-bit analog-to-digital (A/D) CONVERTER CIRCUIT connected to said second AMPLIFIER CIRCUIT for performing 1-bit quantization operation on said QL1 signal;

a third one-bit analog-to-digital (A/D) CONVERTER CIRCUIT connected to said third AMPLIFIER CIRCUIT for performing 1-bit quantization operation on said IL2 signal;

a fourth one-bit analog-to-digital (A/D) CONVERTER CIRCUIT connected to said fourth AMPLIFIER CIRCUIT for performing 1-bit quantization operation on said QL2 signal;

a fifth one-bit analog-to-digital (A/D) CONVERTER CIRCUIT connected to said fifth AMPLIFIER CIRCUIT for performing 1-bit quantization operation on said IL3 signal;

a sixth one-bit analog-to-digital (A/D) CONVERTER CIRCUIT connected to said sixth AMPLIFIER CIRCUIT for performing 1-bit quantization operation on said QL3 signal;

a first FLIP-FLOP CIRCUIT (FF1) connected to said first one-bit A/D CONVERTER for sampling said IL1 signal, wherein said sampling operation is performed by clocking said IL1 signal through said FF1 at sampling clock (SCLK) rate;

a second FLIP-FLOP CIRCUIT (FF2) connected to said second one-bit A/D CONVERTER for sampling said QL1 signal, wherein said sampling operation is performed by clocking said QL1 signal through said FF2 at sampling clock (SCLK) rate;

a third FLIP-FLOP CIRCUIT (FF3) connected to said third one-bit A/D CONVERTER for sampling said IL2 signal, wherein said sampling operation is performed by clocking said IL2 signal through said FF3 at sampling clock (SCLK) rate;

a fourth FLIP-FLOP CIRCUIT (FF4) connected to said fourth one-bit A/D CONVERTER for sampling said QL2 signal, wherein said sampling operation is performed by clocking said QL2 signal through said FF4 at sampling clock (SCLK) rate;

a fifth FLIP-FLOP CIRCUIT (FF5) connected to said fifth one-bit A/D CONVERTER for sampling said IL3 signal, wherein said sampling operation is performed by clocking said IL3 signal through said FF5 at sampling clock (SCLK) rate; and

a sixth FLIP-FLOP CIRCUIT (FF6) connected to said sixth one-bit A/D CONVERTER for sampling said QL3 signal, wherein said sampling operation is performed by clocking said QL3 signal through said FF6 at sampling clock (SCLK) rate.

10. The system of claim 2, wherein each said DIGITAL CHANNEL PROCESSING CIRCUIT further comprises:

an L1 TRACKER CIRCUIT for locally generating replica of said C/A code and said P(Y) code modulated on L1 carrier frequency signal, for tracking an L1 satellite signal, and for correlating said locally generated replica of C/A and P(Y) code with the received L1 code for obtaining an estimate of L1 group delay (L1 pseudo-range) and L1 carrier phase;

an L2 TRACKER CIRCUIT connected to said L1 TRACKER CIRCUIT for locally generating replica of said P(Y) code modulated on L2 carrier frequency signal, for tracking an L2 satellite signal, and for correlating said locally generated replica of P(Y) code with the received L2 code for obtaining an estimate of L2 group delay (L2 pseudo-range) and L2 carrier phase;

an L3 TRACKER CIRCUIT connected to said L2 TRACKER CIRCUIT for locally generating replica of said C/A code modulated on L3 carrier frequency signal, for tracking an L3 satellite signal, and for correlating said locally generated replica of C/A code with the received L3 code for obtaining an estimate of L3 group delay (L3 pseudo-range) and L3 carrier phase; and

a MICROPROCESSOR CIRCUIT system connected to said L1 TRACKER CIRCUIT, to said L2 TRACKER CIRCUIT, and to said L3 TRACKER CIRCUIT;

wherein said L1 TRACKER CIRCUIT is fed by digitized inphase IL1 and quadrature QL1 of L1 signal outputted by said IF PROCESSOR CIRCUIT; and

wherein said L2 TRACKER CIRCUIT is fed by digitized inphase IL2 and quadrature QL2 of L2 signal outputted by said IF PROCESSOR CIRCUIT; and

wherein said L3 TRACKER CIRCUIT is fed by digitized inphase IL3 and quadrature QL3 of L3 signal outputted by said IF PROCESSOR CIRCUIT; and

wherein each said L1, L2, and L3 TRACKER CIRCUIT are synchronously clocked by said SCLK signal and synchronously referenced by said MSEC signal to local reference time;

said SCLK and MSEC signals being outputted by said FREQUENCY SYNTHESIZER CIRCUIT; and

wherein said MICROPROCESSOR CIRCUIT system is fed by output signals from said L1 TRACKER CIRCUIT, from said L2 TRACKER CIRCUIT, and from said L3 TRACKER CIRCUIT; and

wherein said L1 TRACKER CIRCUIT, said L2 TRACKER CIRCUIT, and said L3 TRACKER CIRCUIT are fed by CONTROL signal generated by said MICROPROCESSOR CIRCUIT.

11. The system of claim 10, wherein said L1 TRACKER CIRCUIT further comprises:

a CODE GENERATOR CIRCUIT 1 for providing a locally generated replica of C/A code and P(Y) code;

a MULTIPLEXER CIRCUIT 1 connected to said CODE GENERATOR CIRCUIT 1 for selecting a locally generated code C/A or a locally generated P(Y), wherein said MULTIPLEXER CIRCUIT 1 is controlled by CONTROL signal generated by said MICROPROCESSOR SYSTEM;

a carrier numerically controlled oscillator (CARRIER NCO CIRCUIT

     1) connected to said MULTIPLEXER CIRCUIT 1;

a COMPLEX MIXER CIRCUIT 1 connected to said CARRIER NCO CIRCUIT 1 for multiplying outputted by said IF PROCESSOR CIRCUIT digitized inphase IL1 and QL1 signals having carrier frequency with outputted by said CARRIER NCO CIRCUIT 1 inphase and quadrature components of digital carrier;

wherein said CARRIER MIXER CIRCUIT 1 outputs inphase IL1 and quadrature QL1 signals having zero carrier frequency;

a CODE MIXER CIRCUIT 1 connected to said COMPLEX MIXER CIRCUIT 1, connected to said CODE GENERATOR CIRCUIT 1, and connected to said CARRIER NCO CIRCUIT 1 for code correlating said COMPLEX MIXER CIRCUIT 1 output signals with said locally generated replica of C/A code;

wherein when said L1 TRACKER CIRCUIT'"'"'s carrier tracking loop is closed via said CARRIER NCO CIRCUIT 1 the input to said CODE MIXER CIRCUIT 1 represents the satellite signal L1 C/A code; and

wherein said CODE MIXER CIRCUIT 1 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

a block CORRELATORS CIRCUIT 1 connected to said CODE MIXER CIRCUIT 1 for integrating said early, punctual and late samples of said autocorrelation function;

wherein said CORRELATORS CIRCUIT 1 output signal is fed to said MICROPROCESSOR CIRCUIT system at a rate of L1 C/A code epoch, and wherein said MICROPROCESSOR CIRCUIT uses said CORRELATORS CIRCUIT 1 output signal to develop feedback signals for the carrier tracking loop and for the code tracking loop; and

a code numerically controlled oscillator (CODE NCO CIRCUIT

     1) connected to said block CORRELATORS CIRCUIT 1 and connected to said CODE GENERATOR CIRCUIT 1 for providing a clocking signal at C/A code rate and for providing a clocking signal at P code rate, said C/A code clocking rate and said P code clocking rate driving said CODE GENERATOR CIRCUIT 1;

said CODE NCO CIRCUIT 1 also providing a mechanism for aligning said locally generated replica of C/A code with said incoming satellite C/A code.

12. A method for optimum correlation processing of at least three signals M1, M2, and M3 emanating from the same satellite belonging to the satellite positioning system (SPS), said method comprising the steps of:

receiving and preparing for processing each said M1, M2, and M3 signal by a RECEIVING CIRCUIT; and

processing each said M1, M2, and M3 signal in order to perform the code and carrier measurements to solve for user'"'"'s position, velocity, and time coordinate by a DIGITAL SIGNAL PROCESSING CIRCUIT;

wherein the availability of at least three M1, M2, and M3 signals increases the accuracy in finding the user'"'"'s position, velocity, and time coordinate.

13. A method for optimum correlation processing of at least three L1, L2, and L3 signals received from a SPS satellite by a SPS RECEIVER, said method comprising the steps of:

receiving a known C/A code and a known P(Y) code modulated on L1 carrier frequency signal from at least one satellite by a RECEIVING CIRCUIT;

receiving a known P(Y) code modulated on L2 carrier frequency signal from at least one satellite by a RECEIVING CIRCUIT;

receiving a known C/A code modulated on L3 carrier frequency from at least one satellite by a RECEIVING CIRCUIT;

locally generating replica of said C/A code modulated on L1 carrier frequency by at least one DIGITAL CHANNEL PROCESSING CIRCUIT;

locally generating replica of said C/A code modulated on L3 carrier frequency by at least one DIGITAL CHANNEL PROCESSING CIRCUIT;

locally generating replica of said P(Y) code modulated on L1 carrier frequency by at least one DIGITAL CHANNEL PROCESSING CIRCUIT;

locally generating replica of said P(Y) code modulated on L2 carrier frequency by at least one DIGITAL CHANNEL PROCESSING CIRCUIT;

correlating the locally generated replica of C/A code with the received L1 code for obtaining an estimate of L1 group delay (L1 pseudo-range) and L1 carrier phase by at least one DIGITAL CHANNEL PROCESSING CIRCUIT;

correlating the locally generated replica of P(Y) code with the received L1 code for obtaining an estimate of L1 group delay (L1 pseudo-range) and L1 carrier phase by at least one DIGITAL CHANNEL PROCESSING CIRCUIT;

correlating the locally generated replica of P(Y) code with the received L2 code for obtaining an estimate of L2 group delay (L2 pseudo-range) and L2 carrier phase by at least one DIGITAL CHANNEL PROCESSING CIRCUIT; and

correlating the locally generated replica of C/A code with the received L3 code for obtaining an estimate of L3 group delay (L3 pseudo-range) and L3 carrier phase by at least one DIGITAL CHANNEL PROCESSING CIRCUIT.