Integrated circuit temperature monitoring and protection system

• US 5,805,403 A
• Filed: 03/28/1996
• Issued: 09/08/1998
• Est. Priority Date: 03/28/1996
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: 3COM Limited (HP Inc.)
• Inventors: Chemla, Guy
• Primary Examiner(s): Young, Brian K.
• Assistant Examiner(s): SHERRY, MICHAEL JUDE
• Application Number:
  US08/620,801
• Time in Patent Office: 894 Days
• Field of Search: 361/103, 257/467, 337/300-302, 337/303, 337/304, 364/490-491, 364/483, 364/557
• US Class Current: 361/103
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system of monitoring and protecting integrated circuits against damage due to over temperature conditions functions to monitor the temperature of an IC and either shut down its input clock signal or assert its reset line if case temperatures rise to high. Heat dissipated by an integrated circuit is sensed by a temperature sensor. The temperature sensor is thermally coupled to the integrated circuit via thermal glue or other thermally conductive means. The output of temperature sensor is input to temperature sensor circuitry which converts the low level output of the temperature sensor into a signal that can be read by a processor. The processor is suitable programmed to monitor the output of temperature sensor circuitry. When the temperature of the integrated circuit rises past a predetermined threshold value, the processor outputs a control signal to the clock generator circuitry causing it to switch off its clock signal input by the integrated circuit or asserts the chips reset line. Either action should prevent any further temperature rise of the chip. Other embodiments include monitoring multitude integrated circuits and placing the sensing components within the chip itself. In addition, an embodiment is disclosed that utilizes the JTAG interface standard included in many integrated circuits to transmit temperature information to the processor. In addition, the present invention can be used to generate heat maps of circuit boards, useful during prototyping and in the management of real systems.

Claims

1. A system of monitoring the temperature of an integrated circuit, the system comprising:

a temperature sensor thermally coupled to said integrated circuit;

temperature sensor circuitry coupled to said temperature sensor, said temperature sensor circuitry operative to generate a signal in proportion to the temperature of said integrated circuit;

a processor coupled to said temperature sensor circuitry, said processor operative to monitor the output of said temperature sensor circuitry; and

means for holding the integrated circuit in reset, the integrated circuit being held in reset upon the temperature of said integrated circuit exceeding a predetermined threshold level thus protecting said integrated circuit from damage due to an over temperature condition.

2. The system according to claim 1, wherein said temperature sensor is coupled to said temperature sensor circuitry using thermally conductive glue.

3. The system according to claim 1, wherein said temperature sensor is integral with said temperature sensor circuitry.

4. A system of monitoring the temperature of an integrated circuit, said system situated within said integrated circuit, the system comprising:

a switch having an input, an output and a control input;

a temperature sensor thermally coupled to said integrated circuit;

temperature sensor circuitry coupled to said temperature sensor, said temperature sensor circuitry operative to generate a signal in proportion to the temperature of said integrated circuit;

clock control circuitry coupled to said temperature sensor circuitry, said clock control circuitry operative to monitor the output of said temperature sensor circuitry; and

wherein said switch is responsive to a command issued by said clock control circuitry upon the temperature of said integrated circuit rising above a predetermined threshold level.

5. The system according to claim 4, wherein said clock circuitry generates an over temperature output signal.

6. The system according to claim 4, wherein said temperature sensor and said temperature sensor circuitry are situated within said integrated circuit.

7. A system for monitoring the temperature of a plurality of integrated circuits, coupled together in cascaded fashion including a first integrated circuit and a last integrated circuit, the system comprising:

a temperature sensor internal to said integrated circuit;

temperature sensor circuitry coupled to said temperature sensor, said temperature sensor circuitry internal to each integrated circuit and operative to generate a signal in proportion to the temperature thereof;

JTAG interface circuitry within each integrated circuit, said JTAG interface circuitry having an input and an output, the output of said JTAG interface circuitry within each integrated circuit coupled to the input to said JTAG interface circuitry in an integrated circuit located downstream therefrom; and

a processor coupled to the input to said JTAG interface circuitry of the first integrated circuit and to the output of said JTAG interface circuitry of the last integrated circuit, said processor operative to monitor the output of said temperature sensor circuitry utilizing said JTAG interface circuitry in each integrated circuit.

8. The system according to claim 7, further comprising means of halting a clock signal input to said plurality of integrated circuits, said means of halting a clock signal responsive to a command issued by said processor upon the temperature of said plurality of integrated circuits, either singly or in combination, rising above a predetermined threshold level.

9. The system according to claim 7, further comprising means of holding said plurality of integrated circuit in reset, either singly or in combination, said means of holding said plurality of integrated circuit in reset responsive to a command issued by said processor upon the temperature of said plurality of integrated circuits, either singly or in combination, rising above a predetermined threshold level.

10. A method of monitoring the temperature of an integrated circuit, the method comprising the steps of:

providing a switch for controlling the distribution of a clock signal to the integrated circuit, said switch responsive to a command to either open or close;

sensing the temperature of said integrated circuit;

generating a signal in proportion to said temperature of said integrated circuit;

monitoring said signal and comparing it to a predetermined threshold level; and

generating a command to open said switch when said signal exceeds said predetermined threshold level thus stopping the clock to the integrated circuit.

11. A system of monitoring the temperature of an integrated circuit, the system comprising:

a temperature sensor thermally coupled to said integrated circuit;

temperature sensor circuitry coupled to said temperature sensor, said temperature sensor circuitry operative to generate a signal in proportion to the temperature of said integrated circuit;

a processor coupled to said temperature sensor circuitry, said processor operative to monitor the output of said temperature sensor circuitry; and

means for halting a clock signal coupled to the integrated circuit, said means responsive to a command issued by said processor upon the temperature of the integrated circuit exceeding a predetermined threshold level thus protecting said integrated circuit from damage due to an over temperature condition.

12. A method of monitoring the temperature of an integrated circuit, the method comprising the steps of:

sensing the temperature of said integrated circuit;

generating a signal in proportion to said temperature of said integrated circuit;

monitoring said signal and comparing it to a predetermined threshold level; and

holding the integrated circuit in reset upon said signal exceeding said predetermined threshold thus greatly reducing heat generating activity of the integrated circuit.