Circuit and method for converting a pair of input signals into a level-limited output signal

• US 5,805,505 A
• Filed: 12/16/1996
• Issued: 09/08/1998
• Est. Priority Date: 12/16/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wright, Jeffrey P., Zheng, Hua
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/767,181
• Time in Patent Office: 631 Days
• Field of Search: 365/189.05, 326/57, 326/63, 326/68, 326/80, 326/83, 326/87
• US Class Current: 365/189.05
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/01707 in asynchronous circuits

Abstract

A circuit converts first and second input signals having first and second active levels, respectively, into an output signal. The circuit includes first and second input terminals, an output terminal and first and second drive terminals. A first stage of the circuit is coupled to the first input terminal, the first drive terminal and the output terminal. The first stage couples a first impedance between the first drive terminal and the output terminal when the first input signal is at the first active level, and reduces the magnitude of the first impedance for a first predetermined time after the first input signal transitions to the first active level. A second stage is coupled to the second input terminal, the second drive terminal and the output terminal, and couples a second impedance between the second drive terminal and the output terminal when the second input signal is at the second active level. The second stage may reduce the magnitude of the second impedance for a second predetermined time after the second input signal transitions to the second active level.

Claims

1. A circuit that converts first and second input signals having first and second active levels, respectively, into an output signal, the circuit comprising:

first and second input terminals operable to receive said first and second input signals;

an output terminal operable to provide said output signal;

first and second drive terminals;

a first stage that is coupled to said first input terminal, said first drive terminal, and said output terminal, said first stage operable to couple a first impedance between said first drive terminal and said output terminal when said first input signal is at said first active level, said first stage operable to reduce the magnitude of said first impedance for a first predetermined time after said first input signal transitions to said first active level; and

a second stage that is coupled to said second input terminal, said second drive terminal, and said output terminal, said second stage operable to couple a second impedance between said second drive terminal and said output terminal when said second input signal is at said second active level.

2. The circuit of claim 1 wherein said first impedance approximately equals said second impedance.

3. A circuit that converts first and second input signals having first and second active levels, respectively, into an output signal, the circuit comprising:

first and second input terminals operable to receive said first and second input signals;

an output terminal operable to provide said output signal;

first and second supply terminals;

a first stage that is coupled to said first input terminal, said first supply terminal, and said output terminal, said first stage operable to couple a first impedance between said first supply terminal and said output terminal when said first input signal is at said first active level, said first stage operable to reduce the magnitude of said first impedance for a first predetermined time after said first input signal transitions to said first active level; and

a second stage that is coupled to said second input terminal, said second supply terminal, and said output terminal, said second stage operable to couple a second impedance between said second supply terminal and said output terminal when said second input signal is at said second active level, said second stage operable to reduce the magnitude of said second impedance for a second predetermined time after said second data signal transitions to said second active level.

4. The circuit of claim 3 wherein said first and second stages are each operable to respectively reduce said magnitudes of said first and second impedances to less than 100 ohms.

5. A circuit that converts first and second input signals having first and second active levels, respectively, into an output signal, the circuit comprising:

first and second input terminals;

an output terminal;

first and second supply terminals;

a first switch having a control terminal, a first switch terminal coupled to said first supply terminal, and a second switch terminal;

a second switch having a control terminal coupled to said first input terminal, a first switch terminal coupled to said second switch terminal of said first switch, and a second switch terminal coupled to said output node;

a third switch having a control terminal coupled to said second input terminal, a first switch terminal coupled to said output node, and a second switch terminal;

a fourth switch having a control terminal, a first switch terminal coupled to said second switch terminal of said third switch, and a second switch terminal coupled to said second supply terminal;

a first load coupled in parallel with said first switch;

a second load coupled in parallel with said fourth switch;

a first timer having an input terminal coupled to said first input terminal and having an output terminal coupled to said control terminal of said first switch, said first timer operable to activate said first switch for a first predetermined time after said first input signal transitions to said first active level; and

a second timer having an input terminal coupled to said second input terminal and having an output terminal coupled to said control terminal of said fourth switch, said second timer operable to activate said fourth switch for a second predetermined time after said second input signal transitions to said second active level.

6. The circuit of claim 5 wherein:

said first timer comprises a first monostable circuit coupled between said input terminal and said output terminal of said first timer, said first monostable circuit operable to generate a pulse having a duration equal to said first predetermined time; and

said second timer comprises a second monostable circuit coupled between said input terminal and said output terminal of said second timer, said second monostable circuit operable to generate a pulse having a duration equal to said second predetermined time.

7. The circuit of claim 5 wherein:

said first timer comprises a first delay circuit coupled between said input terminal and said output terminal of said first timer, said first delay circuit operable to delay said first input signal for said first predetermined time; and

said second timer comprises a second delay circuit coupled between said input terminal and said output terminal of said second timer, said second delay circuit operable to delay said second input signal for said second predetermined time.

8. The circuit of claim 5, further comprising:

a third supply terminal;

a first overdrive module coupled between said output terminal of said first timer and said control terminal of said first switch, said first overdrive module having a power terminal coupled to said third supply terminal;

a second overdrive module coupled between said first input terminal and said control terminal of said second switch, said second overdrive module having A power terminal coupled to said third supply terminal;

wherein said first supply terminal is coupled to receive a first supply voltage; and

wherein said third supply terminal is coupled to receive a second supply voltage that is greater than said first voltage.

9. The circuit of claim 8 wherein said first and second overdrive modules each comprise an inverter coupled between said output terminal of said respective first and second timer and said control terminal of said respective first and fourth transistor, said inverter having a power terminal coupled to said third supply terminal.

10. A circuit that converts first and second input signals into an output signal, the circuit comprising:

first and second input terminals operable to receive said first and second input signals;

an output terminal operable to provide said output signal;

first and second supply terminals;

a first switch having a control terminal, a first switch terminal coupled to said first supply terminal, and a second switch terminal coupled to said output terminal;

a second switch having a control terminal coupled to said first input terminal, a first switch terminal coupled to said first supply terminal, and a second switch terminal;

a third switch having a control terminal, a first switch terminal coupled to said output node, and a second switch terminal coupled to said second supply terminal;

a fourth switch having a control terminal coupled to said second input terminal, a first switch terminal, and a second switch terminal coupled to said second supply terminal;

a first load serially coupled between said second switch terminal of said second switch and said output terminal;

a second load serially coupled between said first switch terminal of said fourth switch and said output terminal;

a first timer having an input terminal coupled to said first input terminal and having an output terminal coupled to said control terminal of said first switch, said first timer operable to activate said first switch for a first predetermined time after said first input signal transitions to said first active level; and

a second timer having an input terminal coupled to said second input terminal and having an output terminal coupled to said control terminal of said third switch, said second timer operable to activate said third switch for a second predetermined time after said second input signal transitions to said second active level.

11. The circuit of claim 10 wherein:

said first timer comprises a first monostable circuit coupled between said input terminal and said output terminal of said first timer, said first monostable circuit operable to generate a pulse having a duration equal to said first predetermined time; and

said second timer comprises a second monostable circuit coupled between said input terminal and said output terminal of said second timer, said second monostable circuit operable to generate a pulse having a duration equal to said second predetermined time.

12. The circuit of claim 10, further comprising:

a third supply terminal;

a first overdrive module coupled between said output terminal of said first timer and said control terminal of said first switch, said first overdrive module having a power terminal coupled to said third supply terminal;

a second overdrive module coupled between said first input terminal and said control terminal of said second switch, said second overdrive module having a power terminal coupled to said third supply terminal;

wherein said first supply terminal is coupled to receive a first supply voltage; and

wherein said third supply terminal is coupled to receive a second supply voltage that is greater than said first voltage.

13. The circuit of claim 10 wherein said first, second, third, and fourth switches each comprise an n-channel transistor.

14. A memory device, comprising:

first and second supply terminals;

address, data, and command busses;

a data pin coupled to said data bus;

a bank of memory cells;

an address decoder coupled to said address bus and said memory bank;

a control circuit coupled to said command bus and to said address decoder;

a read/write circuit coupled to said address decoder, control circuit, and memory bank, said read/write circuit operable to generate during a read cycle first and second data signals having first and second active levels respectively; and

a data input/output circuit coupled to said data bus, read/write circuit, and control circuit, said data input/output circuit including a data output driver that includes,

first and second input terminals coupled to said read/write circuit,

an output terminal coupled to said data pin via said data bus,

a first driver stage that is coupled to said first input terminal, said first supply terminal, and said output terminal, said first stage operable to couple a first impedance between said first supply terminal and said output terminal when said first data signal is at said first active level, said first stage operable to reduce the magnitude of said first impedance for a first predetermined time after said first data signal transitions to said first active level, and

a second stage that is coupled to said second input terminal, said second supply terminal, and said output terminal, said second stage operable to couple a second impedance between said second supply terminal and said output terminal when said second data signal is at said second active level, said second stage operable to reduce the magnitude of said second impedance for a second predetermined time after said second data signal transitions to said second active level.

15. The memory device of claim 14 wherein:

said first stage comprises,

a first switch having a control terminal, a first switch terminal coupled to said first supply terminal, and a second switch terminal,

a second switch having a control terminal coupled to said first input terminal, a first switch terminal coupled to said second switch terminal of said first switch, and a second switch terminal coupled to said output node,

a first load shunting said first switch, and

a first timer having an input terminal coupled to said first input terminal and having an output terminal coupled to said control terminal of said first switch, said first timer operable to activate said first switch for said first predetermined time; and

said second stage comprises,

a third switch having a control terminal coupled to said second input terminal, a first switch terminal coupled to said output node, and a second switch terminal,

a fourth switch having a control terminal, a first switch terminal coupled to said second switch terminal of said third switch, and a second switch terminal coupled to said second supply terminal,

a second load shunting said fourth switch, and

a second timer having an input terminal coupled to said second input terminal and having an output terminal coupled to said control terminal of said fourth switch, said second timer operable to activate said fourth switch for said second predetermined time.

16. The memory device of claim 15 wherein:

said first timer comprises a first one-shot device coupled between said input terminal and said output terminal of said first timer, said first one-shot device operable to generate a pulse having a duration equal to said first predetermined time; and

said second timer comprises a second one-shot device coupled between said input terminal and said output terminal of said second timer, said second one-shot device operable to generate a pulse having a duration equal to said second predetermined time.

17. The memory device of claim 15 wherein:

said first timer comprises a first delay circuit coupled between said input terminal and said output terminal of said first timer, said first delay circuit operable to delay said data input signal for said first predetermined time; and

said second timer comprises a second delay circuit coupled between said input terminal and said output terminal of said second timer, said second delay circuit operable to delay said data-complement signal for said second predetermined time.

18. The memory device of claim 15, further comprising:

a charge pump having an input terminal coupled to said first supply terminal and having an output terminal; and

wherein said first stage comprises,

a first overdrive module coupled between said output terminal of said first timer and said control terminal of said first switch, said first module having a power terminal coupled to said output terminal of said charge pump, and

a second overdrive module coupled between said first input terminal and said control terminal of said second switch, said second module having a power terminal coupled to said output terminal of said charge pump.

19. The memory device of claim 14 wherein:

said first stage comprises,

a first switch having a control terminal, a first switch terminal coupled to said first supply terminal, and a second switch terminal coupled to said output terminal,

a second switch having a control terminal coupled to said first input terminal, a first switch terminal coupled to said first supply terminal, and a second switch terminal,

a first load serially coupled between said second switch terminal of said second switch and said output terminal, and

a first timer having an input terminal coupled to said first input terminal and having an output terminal coupled to said control terminal of said first switch, said first timer operable to activate said first switch for said first predetermined time, and

said second stage comprises,

a third switch having a control terminal, a first switch terminal coupled to said output node, and a second switch terminal coupled to said second supply terminal,

a fourth switch having a control terminal coupled to said second input terminal, a first switch terminal, and a second switch terminal coupled to said second supply terminal,

a second load serially coupled between said first switch terminal of said fourth switch and said output terminal, and

a second timer having an input terminal coupled to said second input terminal and having an output terminal coupled to said control terminal of said third switch, said second timer operable to activate said third switch for said second predetermined time.

20. The memory device of claim 19 wherein:

said first timer comprises a first pulse generator circuit coupled between said input terminal and said output terminal of said first timer, said first pulse generator operable to generate a pulse having a duration equal to said first predetermined time; and

said second timer comprises a second pulse generator coupled between said input terminal and said output terminal of said second timer, said second pulse generator operable to generate a pulse having a duration equal to said second predetermined time.

21. The memory device of claim 19 wherein said first, second, third, and fourth switches each comprise an n-channel transistor.

22. A computer system, comprising:

a data input device;

a data output device; and

computing circuitry coupled to said data input and output devices, said computing circuitry including a memory device that includes,

first and second supply terminals,

address, data, and command busses,

a data pin coupled to said data bus,

a bank of memory cells,

an address decoder coupled to said address bus and said memory bank,

a control circuit coupled to said command bus and to said address decoder,

a read/write circuit coupled to said address decoder, control circuit, and memory bank, said read/write circuit operable to generate during a read cycle first and second data signals having first and second active levels respectively, and

a data input/output circuit coupled to said data bus, read/write circuit, and control circuit, said data input/output circuit including a data output driver that includes,

first and second input terminals coupled to said read/write circuit,

an output terminal coupled to said data pin via said data bus,

a first driver stage that is coupled to said first input terminal, said first supply terminal, and said output terminal, said first stage operable to couple a first impedance between said first supply terminal and said output terminal when said first data signal is at said first active level, said first stage operable to reduce the magnitude of said first impedance for a first predetermined time after said first data signal transitions to said first active level, and

a second stage that is coupled to said second input terminal, said second supply terminal, and said output terminal, said second stage operable to couple a second impedance between said second supply terminal and said output terminal when said second data signal is at said second active level, said second stage operable to reduce the magnitude of said second impedance for a second predetermined time after said second data signal transitions to said second active level.

23. The computer system of claim 22 wherein:

said first stage comprises,

a first switch having a control terminal, a first switch terminal coupled to said first supply terminal, and a second switch terminal,

a second switch having a control terminal coupled to said first input terminal, a first switch terminal coupled to said second switch terminal of said first switch, and a second switch terminal coupled to said output node,

a first load shunting said first switch, and

a first timer having an input terminal coupled to said first input terminal and having an output terminal coupled to said control terminal of said first switch, said first timer operable to activate said first switch for said first predetermined time; and

said second stage comprises,

a third switch having a control terminal coupled to said second input terminal, a first switch terminal coupled to said output node, and a second switch terminal,

a fourth switch having a control terminal, a first switch terminal coupled to said second switch terminal of said third switch, and a second switch terminal coupled to said second supply terminal,

a second load shunting said fourth switch, and

a second timer having an input terminal coupled to said second input terminal and having an output terminal coupled to said control terminal of said fourth switch, said second timer operable to activate said fourth switch for said second predetermined time.

24. The computer system of claim 22 wherein:

said first stage comprises,

a first switch having a control terminal, a first switch terminal coupled to said first supply terminal, and a second switch terminal coupled to said output terminal,

a second switch having a control terminal coupled to said first input terminal, a first switch terminal coupled to said first supply terminal, and a second switch terminal,

a first load serially coupled between said second switch terminal of said second switch and said output terminal, and

a first timer having an input terminal coupled to said first input terminal and having an output terminal coupled to said control terminal of said first switch, said first timer operable to activate said first switch for said first predetermined time; and

said second stage comprises,

a third switch having a control terminal, a first switch terminal coupled to said output node, and a second switch terminal coupled to said second supply terminal,

a fourth switch having a control terminal coupled to said second input terminal, a first switch terminal, and a second switch terminal coupled to said second supply terminal,

a second load serially coupled between said first switch terminal of said fourth switch and said output terminal, and

a second timer having an input terminal coupled to said second input terminal and having an output terminal coupled to said control terminal of said third switch, said second timer operable to activate said third switch for said second predetermined time.

25. A method for driving a node with an output signal, comprising:

receiving a first input signal having a first active level;

receiving a second input signal having a second active level;

coupling a first drive signal to said node through a first impedance when said first input signal is at said first active level;

coupling a second drive signal to said node through a second impedance when said second input signal is at said second active level; and

increasing the magnitude of said second impedance at a first predetermined time after said second input signal attains said second active level.

26. The method of claim 25 wherein said coupling a second drive signal and said increasing the magnitude comprise enabling first and second parallel electrical paths between said second drive signal and said node during said first predetermined time, and disabling one of said first and second paths after said first predetermined time expires.

27. The method of claim 25, further comprising increasing the magnitude of said first impedance at a second predetermined time after said first input signal attains said first active level.

28. The method of claim 25, further comprising:

increasing the magnitude of said first impedance at a second predetermined time after said first input signal attains said first active level;

wherein said coupling a first drive signal and said increasing the magnitude of said first impedance include enabling first and second parallel electrical paths between said first drive signal and said node during said second predetermined time, and disabling one of said first and second paths after said second predetermined time expires; and

wherein said coupling a second drive signal and said increasing the magnitude of said second impedance include enabling third and fourth parallel electrical paths between said second drive signal and said node during said first predetermined time, and disabling one of said third and fourth paths after said first predetermined time expires.