Network monitoring system for cell delay variation

• US 5,805,602 A
• Filed: 10/01/1996
• Issued: 09/08/1998
• Est. Priority Date: 09/25/1995
• Status: Expired due to Term

• Current Assignee: Verizon Patent and Licensing Incorporated (Verizon Communications Inc.)
• Original Assignee: Bell Atlantic Network Services, Inc. (Verizon Communications Inc.)
• Inventors: Cloutier, Leo, Curtis, David C., Curtis, Kathleen P., Denunzio, David D., Reed, William P., Wolak, Robert A.
• Primary Examiner(s): Patel, Ajit
• Application Number:
  US08/725,653
• Time in Patent Office: 707 Days
• Field of Search: 370/474, 370/476, 370/395, 370/397, 370/503, 370/506, 370/508, 370/516, 370/517, 370/519, 375/371, 375/372, 348/423, 348/474, 348/500, 348/432, 348/434, 348/497
• US Class Current: 370/516
• CPC Class Codes: H04L 2012/5638 Services, e.g. multimedia, GOS, QOS
• CPC Class Codes: H04L 2012/5649 Cell delay or jitter
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4344 Remultiplexing of multiplex streams, e.g. by modifying time stamps or remapping the packet identifiers
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer
• CPC Class Codes: H04N 21/64307 ATM
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

An arrangement (apparatus and method) for monitoring jitter caused during transport of digitally-coded information in a packet switched network, and for managing network operations in accordance with the detected jitter. The detected jitter is used to determine whether corrective action is necessary, such as rerouting network traffic, or performing network maintenance. The disclosed arrangement detects program clock reference (PCR) values from an MPEG-encoded transport stream, whereby each pair of PCR values represents an expected arrival time of a corresponding stream segment. An actual arrival time for the corresponding stream segment is determined in response to detection of the corresponding PCR values and an independent clock signal. The expected arrival time of the stream segment and the actual arrival time are correlated with an accumulation of expected and actual arrivaimes of previously-received data packet stream segments in order to determine the jitter in the digital data stream. The jitter is corrected by a combination of adaptive buffering techniques and restamping the PCR value with corrected values coinciding with the actual arrival time of the stream segments.

Claims

1. An apparatus for minimizing jitter caused during transmission of a data packet stream, comprising:

a time stamp detector detecting time stamp values within said data packet stream, each time stamp value representing an expected arrival time of a corresponding data packet stream segment;

a timing circuit, responsive to a clock signal, for determining an actual arrival time for each said corresponding data packet stream segment;

a detecting circuit detecting jitter in each data packet stream segment by executing a correlation of the corresponding expected arrival time and the corresponding actual arrival time with an accumulation of expected and actual arrival times of previously-received data packet stream segments; and

a data packet stream correction circuit outputting said data packet stream as a corrected data packet stream having time stamp values adjusted in response to said correlation.

2. An apparatus as in claim 1, wherein said data packet stream correction circuit comprises a timing restamp module replacing said time stamp values with corrected time stamp values in accordance with said correlation.

3. An apparatus as in claim 2, wherein said data packet stream correction circuit further comprises a buffer circuit receiving said time stamp values.

4. An apparatus as in claim 3, wherein said buffer circuit has an output data rate controlled in response to said correlation.

5. An apparatus as in claim 3, wherein said buffer circuit selectively adjusts a spacing between packets in said data packet stream in accordance with said correlation.

6. An apparatus as in claim 3, further comprising an independent clock source outputting said clock signal.

7. An apparatus as in claim 1, wherein said data packet stream is received in MPEG format, said time stamp detector detecting said time stamp values as program clock reference (PCR) values from an MPEG stream having a selected program identifier (PID) value.

8. An apparatus as in claim 7, wherein said data packet stream correction circuit comprises a buffer circuit receiving said MPEG stream for adjusting said time stamp values.

9. An apparatus as in claim 8, wherein said buffer circuit has an output data rate controlled in response to said correlation.

10. An apparatus as in claim 8, wherein said buffer circuit selectively adjusts a spacing between packets in said MPEG stream in accordance with said correlation.

11. An apparatus as in claim 8, wherein said buffer circuit adjusts said time stamp values in accordance with said corresponding correlation and a buffer fullness ratio.

12. An apparatus as in claim 8, wherein said data packet stream correction circuit further comprises a timing restamp module replacing said PCR values in said MPEG stream with corrected PCR values in accordance with said correlation.

13. An apparatus as recited in claim 7, wherein said data packet stream correction circuit comprises a timing restamp module replacing said PCR values in said MPEG stream with corrected PCR values in accordance with said correlation.

14. An apparatus as in claim 1, wherein said detecting circuit comprises a least square error calculator for calculating a least square error from the expected and actual arrival times of said previously received data packet stream segments.

15. An apparatus as in claim 14, wherein said detecting circuit further comprises a jitter calculator calculating said detected jitter in response to said actual arrival time and a desired actual arrival time generated in response to said expected arrival time and the least squared error.

16. An apparatus as in claim 14, wherein said detecting circuit further comprises a restamp calculation circuit outputting a restamp value to said timing restamp module in response to said expected arrival time and the least square error.

17. An apparatus as recited in claim 1, said timing circuit comprising an independent clock source generating said clock signal.

18. An apparatus as recited in claim 1, further comprising an ATM input processor outputting said data packet stream from an ATM cell stream having a selected virtual path identifier.

19. An apparatus as recited in claim 18, further comprising an ATM output processor outputting a second ATM cell stream carrying said corrected data packet stream.

20. An apparatus as recited in claim 1, further comprising a data interface for supplying the calculated jitter to a control center managing operations of a network transporting said data packet stream, and for supplying a correction signal from said control center to said data packet stream correction circuit, the correction circuit outputting said corrected data packet stream in response to said correction signal.

21. A method for measuring jitter in a transport stream of MPEG-encoded data packets, comprising the steps of:

detecting program clock reference (PCR) values from the transport stream, each PCR value identifying an expected arrival time of a corresponding portion of said transport stream;

identifying an actual arrival time for each said portion of said transport stream in accordance with a clock signal independent from the transport stream; and

calculating said jitter based on a correlation of the corresponding expected and actual arrival times with an accumulation of respective expected and actual arrival times of prior portions of the transport stream.

22. The method of claim 21, further comprising the steps of:

receiving said MPEG-encoded data packets from an asynchronous transfer mode (ATM) stream of cells; and

selecting at least one of said MPEG streams in accordance with a selected program identifier (PID) value.

23. The method of claim 21, wherein said calculating step comprises:

calculating a least square error of the accumulation of respective expected and actual arrival times of prior portions of the transport stream;

determining a desired actual arrival time in response to the expected arrival time for said each portion of the transport stream and the least square error; and

comparing the desired actual arrival time with the actual arrival time for said each portion of the transport stream to determine said jitter.

24. The method of claim 23, further comprising correcting the jitter in response to a comparison between the expected arrival time and the least square error.

25. The method of claim 21, wherein the detecting, identifying, and calculating steps each are executed at a network node, the calculating further comprising supplying the calculated jitter from the node to a control center managing operations of a network transporting the transport stream.

26. The method of claim 25, further comprising correcting said jitter in response to a correction signal from the control center.

27. The method of claim 25, further comprising performing network operations at the network control center to control transport of the transport stream in response to the calculated jitter.

28. The method as in claim 27, wherein said step of performing network operations comprises the step of routing traffic from the network node.

29. A method as in claim 27, wherein said step of performing network operations further comprises the step of initiating a service request in a work force management system portion of the operational support system.

30. A method as in claim 27, wherein said step of performing network operations comprises the step of initiating a service request in a work force management system portion of the operational support system.

31. A method as in claim 27, wherein said step of performing network operations comprises the step of initiating a request for creation of new capacity for the network.

32. A method as in claim 27, wherein said step of performing network operations comprises the steps of:

outputting a jitter correction control signal to the network node in response to the detected jitter; and

correcting the jitter at the network node in response to the jitter correction control signal.

33. A system for monitoring jitter in a packet switched network, comprising:

a plurality of monitors each comprising;

(a) a packet demultiplexer selecting a data packet stream from the packet switched network and outputting a digital data stream from the selected data packet stream;

(b) a time stamp detector detecting time stamp values located within said digital data stream and representing an expected arrival time of a corresponding digital data stream segment,

(c) a timing circuit, responsive to a clock signal, determining an actual arrival time for each said corresponding digital data stream segment, and

(d) a detecting circuit for calculating a jitter value for each digital data stream segment on the basis of the corresponding expected and actual arrival times; and

an operational support system receiving said detected jitter values from the monitors and managing operations of the packet switched network.

34. A system as in claim 33, wherein:

said operational support system outputs at least one correction signal in response to the detected jitter values, and

each of said monitors further comprises a data stream correction circuit, responsive to the at least one correction signal, receiving the digital data stream and outputting a corrected digital data stream having time stamps identifying an expected arrival time substantially coinciding with an actual arrival time of each corresponding digital data stream segment of said corrected digital data stream.

35. A system as in claim 34, wherein said data stream correction circuit comprises a timing restamp module replacing said time stamps with corrected time stamps in accordance with said detected jitter, and a buffer circuit receiving said digital data stream for adjusting said actual arrival time of each said corresponding digital data stream segment in accordance with said detected jitter.

36. A system as in claim 35, wherein said buffer circuit has an output data rate controlled in response to said detected jitter.

37. A system as in claim 35, wherein said buffer circuit selectively adjusts a spacing between packets in said digital data stream in accordance with said detected jitter.

38. A system as in claim 35, further comprising an independent clock source outputting said clock signal.

39. A system as in claim 33, wherein said digital data stream is output from said packet demultiplexer in MPEG format, said time stamp detector detecting said. time stamp values as program clock reference (PCR) values from an MPEG stream having a selected program identifier (PID) value.

40. A system as in claim 39, wherein said monitors each further comprise a correction circuit having a buffer circuit that receives the corresponding MPEG stream and adjusts the actual time duration of each said corresponding digital data stream segment in accordance with a timing adjustment signal from the operational support system.

41. A system as in claim 40, wherein said buffer circuit has an output data rate controlled in response to said timing adjustment signal.

42. A system as in claim 40, wherein said buffer circuit selectively adjusts a spacing between packets in said MPEG stream in accordance with said timing adjustment signal.

43. A system as in claim 40, wherein said buffer circuit adjusts said time duration in accordance with said timing adjustment signal and a buffer fullness ratio.

44. A system as in claim 40, wherein said correction circuit further comprises a timing restamp module replacing said PCR values in said MPEG stream with corrected PCR values in accordance with said timing adjustment signal.

45. A system as in claim 33, wherein said packet demultiplexer comprises an ATM input processor outputting said digital data stream from an ATM cell stream having a selected virtual path identifier.

46. A system as in claim 45, said monitors each further comprising an ATM output processor outputting a second ATM cell stream carrying a corrected digital data stream.

47. A system as in claim 33, wherein the operations support system initiates corrective measures if said detected jitter values exceed a predetermined threshold.

48. A system as in claim 47, wherein the operational support system comprises a router that reroutes traffic in the packet switched network in response to the detected jitter values.

49. A system as in claim 47, wherein said corrective measures include at least one of rerouting network traffic, performing maintenance on one of a plurality of network nodes, and correcting the detected jitter at the one node.

50. A system as in claim 33, wherein the operations support system comprises:

a routing processor assigning each of the data packet streams a virtual path through selected nodes of the packet switched network, the routing processor rerouting at least a portion of a group of data packet streams passing through one of said selected nodes in accordance with corresponding detected jitter values; and

a network element management system for managing corrective action to be performed on said one selected node in accordance with said corresponding detected jitter values.