Emulation devices, systems, and methods

• US 5,805,792 A
• Filed: 03/21/1997
• Issued: 09/08/1998
• Est. Priority Date: 07/31/1989
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ing-Simmons, Nicholas K., Swoboda, Gary L., Simpson, Richard David
• Primary Examiner(s): Hua, Ly
• Application Number:
  US08/821,491
• Time in Patent Office: 536 Days
• Field of Search: 371/22.3, 371/16.2, 371/15.1, 371/16.1, 371/22.4, 371/22.1, 395/183.2, 395/183.03, 395/185.06, 395/800, 395/500, 395/183.04, 395/183.01, 395/183.06, 395/183.02, 395/183.05
• US Class Current: 714/28
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 11/3648 using additional hardware

Abstract

An electronic device having addressable storage elements and a bus so that the storage elements are accessible via the bus, an address register connected to the bus, a data register connected to the bus, terminals for serial scan-in and scan-out, a scanable emulation control register coupled to the terminals, and a selecting circuit responsive to bits in the emulation control register for coupling the address register and the data register to the terminals to enable scanning of the address and data registers.

Claims

1. An electronic device, comprising:

a semiconductor chip and an integrated circuit fabricated thereon, the integrated circuit having a boundary and having interior circuitry for running in response to opcodes;

a chip package having terminals electrically connected to said integrated circuit on said chip, including at least a first said terminal and a second said terminal electrically connected to said chip as scan control and test clock terminals respectively, and at least a third one of said terminals electrically connected to said chip as an emulation control terminal;

the interior circuitry including a CROM control read-only memory on-chip having entry points with at least some of the entry points controlled by opcode decodes, and function circuitry responsive to said CROM to execute opcodes and perform functions of said integrated circuit;

a scan interface on-chip including at least a test access port controller state machine responsive to said first terminal, and a first serial scan path associated with the boundary and coupled for clocking to said second terminal, and a second serial scan path associated with said interior function circuitry; and

said scan interface further having control circuitry coupled to respond to at least said third terminal and said scan interface having modes including at least a first mode of BIST built-in self test, a second mode of emulation wherein said interior functional circuitry is coupled to said second scan path for at least single-stepping of opcodes, and a third mode wherein said function circuitry runs normally and decoupled from said second scan path.

3. The electronic device claimed in claim 1 further comprising terminals coupled to said scan interface for scan control, test clock, scan-in, and scan-out and at least one further terminal coupled to said control circuitry for emulation control.

4. The electronic device claimed in claim 1 further comprising terminals coupled to said scan interface for scan control, test clock, scan-in, and scan-out and at least two further terminals coupled to said control circuitry for emulation control.

5. The electronic device claimed in claim 1 further comprising terminals coupled to said scan interface for scan control, test clock, scan-in, and scan-out and at least one further terminal for emulation control input and at least one further terminal for emulation control output.

6. The electronic device claimed in claim 1 further comprising terminals for scan control, test clock, scan-in, and scan-out and at least one further terminal for emulation control output.

2. An electronic device, comprising:

a semiconductor chip having fabricated thereon an integrated circuit having a boundary and having interior functional circuitry for running in response to instructions;

a scan interface on-chip including a state machine responsive to an external input, a first serial scan path associated with the boundary, and a second serial scan path associated with said interior functional circuitry;

said scan interface further including control circuitry having modes including at least a first mode of BIST built-in self test, a second mode of emulation wherein said interior functional circuitry is coupled to said second scan path for at least single-stepping of said instructions, and a third mode wherein said interior functional circuitry runs normally in response to said instructions and is decoupled from said second scan path.

7. A method of operating an integrated circuit having a boundary and having interior functional circuitry for running in response to instructions, and further provided with a first serial scan path associated with the boundary and a second serial scan path associated with said interior functional circuitry, and at least a first terminal and a second terminal electrically connected to said integrated circuit as scan control and test clock terminals respectively, and at least a third terminal electrically connected to said chip as an emulation control terminal, said method comprising the steps of:

operating a scan interface on-chip in alternative modes responsive to said scan control terminal and said emulation control terminal, including;

in a first mode, scan-testing the boundary via the first scan path;

in a second mode, self-testing the interior functional circuitry according to a BIST built-in self test;

in a third mode, coupling said interior functional circuitry to a second scan path according to an emulation method including at least single-stepping of instructions; and

in a fourth mode, decoupling the interior functional circuitry from said second scan path and running the interior functional circuitry normally.