Method and apparatus for performing a vector skip instruction in a data processor

• US 5,805,874 A
• Filed: 04/18/1995
• Issued: 09/08/1998
• Est. Priority Date: 03/31/1993
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Bell, Meltin, Gallup, Michael G., Goke, L. Rodney
• Primary Examiner(s): Treat, William M.
• Application Number:
  US08/425,961
• Time in Patent Office: 1,239 Days
• Field of Search: 395/375, 395/800, 395/379, 395/376, 395/563, 395/800.22
• US Class Current: 712/222
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3802 : Instruction prefetching
• CPC Class Codes: G06F 9/3812 : with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 : using instruction pipelines
• CPC Class Codes: G06F 9/3877 : using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 : controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06N 3/063 : using electronic means

Abstract

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Claims

1. A method for executing an instruction in a data processor, comprising the steps of:

receiving the instruction;

decoding the instruction to provide a plurality of control signals;

providing a plurality of processing elements and a plurality of enable bits, each of the plurality of enable bits corresponding to an associated one of the plurality of processing elements, each of the plurality of enable bits having a first value if its associated one of the plurality of processing elements is in a first state, and having a second value if its associated one of the plurality of processing elements is in a second state;

accessing the plurality of enable bits in response to the plurality of control signals;

determining if any of the plurality of enable bits have the first value; and

causing all of the plurality of processing elements to skip execution of a next instruction if any of the plurality of enable bits in any of the plurality of processing elements have the first value.

2. The method of claim 1 wherein the first state is a disabled state and the second state is an enabled state.

3. The method of claim 2 wherein the instruction has the mnemonic form of "skipnvt".

4. The method of claim 1 wherein the first value is a binary zero and the second value is a binary one.

5. A data processor, comprising:

circuitry for receiving a vector instruction;

a vector engine capable of executing a vector operation in response to the vector instruction, the vector engine comprising a plurality of processing elements, each one of the plurality of processing elements comprising vector control circuitry for controlling operation of that one of the plurality of processing elements, and each one of the plurality of processing elements comprising a storage circuit for storing an indicator;

circuitry which determines if any indicator within any of the plurality of processing elements has a first value; and

circuitry for causing all of the plurality of processing elements to skip execution of a next vector instruction if any indicator within any of the plurality of processing elements has the first value.

6. A data processor as in claim 5, wherein the storage circuit for storing the indicator is a portion of a user programmable register.

7. A data processor as in claim 5, wherein the indicator in each one of the plurality of processing elements also functions as an enable bit for that one of the plurality of processing elements.

8. A method for executing an instruction in a data processor, comprising the steps of:

receiving the instruction, the instruction having an operand;

decoding the instruction to provide a plurality of control signals;

accessing a data value stored in a storage location indicated by the operand of the instruction in response to the plurality of control signals;

adjusting the data value stored in the storage location by an adjust value to generate an adjusted data value;

asserting an enable value corresponding to the storage location, the enable value selectively enabling the storage location to participate in execution of the instruction;

negating a history value corresponding to the storage location, the history value indicating whether the storage location has been used previously in execution of a conditional instruction;

performing a comparison test to compare the adjusted data value with a predetermined value;

executing a next instruction when a result of the comparison test is false; and

skipping execution of the next instruction when a result of the comparison test is true.

9. The method of claim 8 wherein the instruction has the mnemonic form of "dskipe".

10. The method of claim 8 wherein the adjust value is a value of one and the comparison test is an equality test.

11. The method claim 8 wherein the predetermined value is equal to a value of negative one.

12. The method of claim 8 wherein the data value is stored in a scalar register in the data processor.

13. The method of claim 8 wherein the comparison test determines whether the adjusted data value is less than or equal to the predetermined value.

14. The method of claim 8 wherein the step of adjusting comprises the step of:

adding a value of negative one to the data value to generate the adjusted data value.