Computer system and method for replacing obsolete or corrupt boot code contained within reprogrammable memory with new boot code supplied from an external source through a data port

• US 5,805,882 A
• Filed: 07/19/1996
• Issued: 09/08/1998
• Est. Priority Date: 07/19/1996
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Le, Hung Q., DeLisle, David J., Cooper, Patrick R.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): LANGJAHR, DAVID
• Application Number:
  US08/684,413
• Time in Patent Office: 781 Days
• Field of Search: 395/652, 395/552, 207/205, 711/166
• US Class Current: 713/2
• CPC Class Codes: G06F 11/1417 Boot up procedures
• CPC Class Codes: G06F 11/1433 during software upgrading

Abstract

In accordance with the invention, a computer system is provided with a flash read-only-memory (ROM), a microcontroller and a data port. The microcontroller initially owns the flash ROM. The microcontroller further has a separate ROM upon which it can execute boot-up instructions. After booting up, the microcontroller checks the flash ROM contents, preferably by performing a check-sum of the flash ROM contents. If the checksum of the flash ROM contents matches an expected value, the microcontroller releases ownership of the flash ROM to the computer system so that the computer system boots-up as normal. If the microcontroller determines that the flash ROM has become corrupted, the microcontroller accesses the data port and looks for a flash programming protocol. If the protocol is present at the data port, the microcontroller receives the data from the data port and programs the flash ROM accordingly. In this manner, the flash ROM can be updated to a good known state, even if the computer system is not able to boot up due to, among other things, the corruption of the flash ROM.

Claims

1. A computer system, comprising:

a processor;

a system memory coupled to said processor;

an expansion bus coupled to said processor;

a disk drive coupled to said processor for storing data and providing data, said disk drive coupled to said expansion bus;

a data port coupled to said expansion bus;

a reprogrammable memory coupled to said expansion bus, said reprogrammable memory storing a boot code for execution by said processor upon power up of the computer system;

a microcontroller coupled to said expansion bus, to said reprogrammable memory, and to said data port, said microcontroller initially having access to said reprogrammable memory, said microcontroller selectively communicating with a host computer over said data port; and

an integrity checker to check the integrity of said boot code in said reprogrammable memory and to indicate whether the integrity of said boot code has been compromised, wherein if the integrity of said boot code has been compromised upon power up, said microcontroller receives data from said data port and stores said data in said reprogrammable memory as said boot code.

2. The computer system of claim 1, wherein said data being transmitted over said data port is a software update.

3. The computer system of claim 1, wherein said reprogrammable memory is a flash read-only-memory (ROM).

4. The computer system of claim 1, wherein said reprogrammable memory is a non-volatile random-access-memory (NV-RAM).

5. The computer system of claim 1, wherein said reprogrammable memory stores a primary boot code for execution by said processor upon power up of the computer system.

6. The computer system of claim 5, wherein said reprogrammable memory stores a second boot code for execution by said microcontroller upon power up of the computer system.

7. The computer system of claim 5, further comprising an arbitrator coupled to said processor for relinquishing said reprogrammable memory to said processor for executing said primary boot code during the power up of the computer system.

8. The computer system of claim 5, wherein said system memory has a shadow region and wherein said processor copies said primary boot code in said shadow region if said integrity checker indicates that said boot code is valid.

9. The computer system of claim 8, wherein said processor returns control of said reprogrammable memory to said microcontroller after said primary boot code has been shadowed.

10. The computer system of claim 1, wherein said microcontroller further comprises a command parser coupled to said data port.

11. The computer system of claim 10, wherein said command parser executes a command selected from a group consisting of:

memory bank select command;

a status inquiry command;

a block transfer command;

a peek command;

a poke command;

a program memory command;

an erase memory command;

a reset command;

a speed change command; and

a user programmable command.

12. The computer system of claim 1, further comprising a code update system having a memory for storing updated data and a second data port, said code update system transmitting updated data from said second data port to said data port.

13. The computer system of claim 1, wherein said data port is a parallel port.

14. The computer system of claim 1, wherein said microcontroller further comprises a flash programming protocol detector coupled to said data port.

15. The computer system of claim 14, wherein said flash programming protocol detector detects a host sending to target sequence and a target response sequence.

16. The computer system of claim 15, wherein said data port has a busy signal and a select signal, and wherein said target response sequence is performed using the busy and select signals.

17. The computer system of claim 15, wherein said data port has an autofeed signal and an acknowledge signal, and wherein said host sending to target sequence is performed using the autofeed and acknowledge signals.

18. The computer system of claim 1, wherein said integrity checker comprises a checksum generator running on said microcontroller.

19. The computer system of claim 18, wherein said integrity checker operates on an 8051-compatible microcontroller.

20. The computer system of claim 1, wherein said microcontroller is an 8051 compatible microcontroller.

21. A method for updating a boot code of a computer system, said computer system having a processor coupled to a system memory and an expansion bus;

the processor booting the computer system using a boot code, said expansion bus coupled to a data port;

a reprogrammable memory having the boot code; and

a microcontroller which initially has access to said reprogrammable memory after power up;

said microcontroller selectively communicating with a host computer and receiving data over said data port, said method comprising the steps of;

initially accessing the reprogrammable memory with the microcontroller after power-up;

checking the integrity of said boot code in said reprogrammable memory before the processor boots the system; and

if the integrity of said boot code has been compromised, performing the steps of;

receiving data from said data port; and

storing said data in said reprogrammable memory as said boot code; and

booting the computer system using said processor after said checking step and said if step.

22. The method of claim 21, wherein said data receiving step further comprises the step of waiting for a programming protocol to appear at said data port before said data receiving step.

23. The method of claim 22, further comprising the step of decoding commands from said programming protocol.

24. The method of claim 23, wherein said command decoding step further comprises the step of identifying a command selected from a group consisting of:

a memory bank select command;

a status inquiry command;

a block transfer command;

a peek command;

a poke command;

a program memory command;

an erase memory command;

a reset command;

a speed change command; and

a user programmable command.

25. The method of claim 21, wherein said storing step further comprises the step of programming said reprogrammable memory.

26. The method of claim 25, wherein said programming step further comprises the step of bulk erasing said reprogrammable memory before writing the new data to said reprogrammable memory.

27. The method of claim 21, further comprising the step of allowing said processor access to said reprogrammable memory after said storing step.

28. The method of claim 27, wherein said allowing step further comprises the step of shadowing said data from said reprogrammable memory into said system memory.

29. The method of claim 28, further comprising the step of returning control of said reprogrammable memory to said microcontroller.

30. The method of claim 28, further comprising the step of transmitting code update from a second system over a second data port to said data port.

31. The method of claim 30, wherein said transmitting step transmits boot code update to said reprogrammable memory.

32. An apparatus for updating codes for execution by a processor, said processor coupled to an expansion bus, said apparatus comprising:

a reprogrammable memory coupled to said expansion bus, said reprogrammable memory storing a boot code for execution by the processor upon power up of the processor;

a data port coupled to said expansion bus;

a microcontroller coupled to said expansion bus, to said reprogrammable memory, and to said data port, said microcontroller initially having access to said reprogrammable memory, said microcontroller selectively communicating with a host computer over said data port; and

an integrity checker to check the integrity of said boot code in said reprogrammable memory and to indicate whether the integrity of said boot code has been compromised, wherein if the integrity of said boot code has been compromised upon power up, said microcontroller receives data from said data port and stores said data in said reprogrammable memory as said boot code.

33. The apparatus of claim 32, wherein said data being transmitted over said data port is a software update.

34. The apparatus of claim 32, wherein said reprogrammable memory is a flash read-only-memory (ROM).

35. The apparatus of claim 32, wherein said reprogrammable memory is a non-volatile random-access-memory (NV-RAM).

36. The apparatus of claim 32, wherein said reprogrammable memory stores a primary boot code for execution by said processor upon power up of the computer system.

37. The apparatus of claim 36, wherein said reprogrammable memory stores a second boot code for execution by said microcontroller upon power up of the computer system.

38. The apparatus of claim 36, further comprising an arbitrator coupled to said processor for relinquishing said reprogrammable memory to said processor for executing said primary boot code during the power up of the computer system.