Structure and method for mapping interrupt requests in a high-speed CPU interconnect bus system
First Claim
1. A computer bus system connecting a CPU to connected peripheral devices, comprising:
- a plurality of signal lines excluding any interrupt request (IRQ) lines but including address lines between said CPU and said connected peripheral devices, said connected peripheral devices assigning predetermined interrupt signals to predetermined addresses on said address lines and sending said predetermined interrupt signals to said CPU as said predetermined addresses on said address lines; and
an interrupt controller connected to said address lines, said interrupt controller being adapted to decode said predetermined addresses from said connected peripheral devices on said address lines as said predetermined interrupt signals from said connected peripheral devices to said CPU.
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Accused Products
Abstract
A compressed I/O bus system for a general-purpose computer multiplexes 32 bit data and addresses on 32 of 42 dedicated parallel signal paths, and optimizes the bus structure by mapping bus requests made by peripheral devices to "high" memory portions of system RAM not dedicated to other purposes. In one aspect a bus controller is programmable to select translation routines stored in system RAM allowing various models and types of CPUs to be supported. Supported CPUs are interchangeable in the system. In another aspect a default interface attached to the compressed I/O bus of the invention, and translates bus states between the optimized compressed bus and one of an ISA bus or an EISA bus.
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Citations
24 Claims
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1. A computer bus system connecting a CPU to connected peripheral devices, comprising:
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a plurality of signal lines excluding any interrupt request (IRQ) lines but including address lines between said CPU and said connected peripheral devices, said connected peripheral devices assigning predetermined interrupt signals to predetermined addresses on said address lines and sending said predetermined interrupt signals to said CPU as said predetermined addresses on said address lines; and an interrupt controller connected to said address lines, said interrupt controller being adapted to decode said predetermined addresses from said connected peripheral devices on said address lines as said predetermined interrupt signals from said connected peripheral devices to said CPU. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A computer system comprising:
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a CPU; a bus system excluding any interrupt request (IRQ) line but including address lines connecting said CPU to connected peripheral devices, said connected peripheral devices assigning predetermined interrupt signals to predetermined addresses on said address lines and sending said predetermined interrupt signals to said CPU as said predetermined address signals on said address lines; and an interrupt controller connected to said CPU and to said address lines, said interrupt controller being adapted to decode said predetermined addresses from said connected peripheral devices on said address lines as said predetermined interrupt signals from said connected peripheral devices to said CPU. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method for issuing an interrupt request signal from a peripheral device connected to a computer bus having address and data lines and a bus request line, but no interrupt request lines, comprising the steps of:
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(a) claiming use of the computer bus for the peripheral device by issuing a bus request from the peripheral device on the bus request line; (b) assigning said interrupt request signal to a predetermined address on said address lines; (c) the peripheral device issuing said predetermined address on the computer bus as said interrupt request signal for interrupting a system CPU; (d) decoding the issued predetermined address at an interrupt controller connected to the computer bus and to said system CPU; and (e) vectoring the CPU to execute a unique interrupt routine associated with the predetermined address issued by the peripheral device. - View Dependent Claims (22, 23)
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24. A method for reducing pinouts for a computer bus having an interrupt controller coupled to a CPU, comprising the steps of:
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(a) removing all interrupt request lines; (b) assigning predetermined addresses on an address line to unique interrupt routines; (c) adapting the interrupt controller to vector the CPU to the unique interrupt routines pointed to by said predetermined addresses upon receipt of said predetermined addresses on said address line; and (d) adapting peripheral devices connectable to the computer bus to issue at least one of said predetermined addresses in lieu of pulling an interrupt request line to begin an interrupt process.
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Specification