Structure and method for mapping interrupt requests in a high-speed CPU interconnect bus system

• US 5,805,901 A
• Filed: 11/12/1996
• Issued: 09/08/1998
• Est. Priority Date: 07/02/1993
• Status: Expired due to Fees

• Current Assignee: PDACO LIMITED
• Original Assignee: Elonex IP Holdings Limited
• Inventors: Kikinis, Dan, Dornier, Pascal
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US08/753,254
• Time in Patent Office: 665 Days
• Field of Search: 395/500, 395/183.1, 395/860, 395/490, 395/800, 395/430, 395/200.01, 395/556, 395/200.15, 395/290, 395/479, 395/309, 395/281, 395/825, 395/259, 395/740, 395/306, 395/733, 395/285, 345/200, 434/49, 364/DIG. 1, 364/DIG. 2, 340/825.22, 340/825.09
• US Class Current: 710/260
• CPC Class Codes: F02B 2075/027 four
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A compressed I/O bus system for a general-purpose computer multiplexes 32 bit data and addresses on 32 of 42 dedicated parallel signal paths, and optimizes the bus structure by mapping bus requests made by peripheral devices to "high" memory portions of system RAM not dedicated to other purposes. In one aspect a bus controller is programmable to select translation routines stored in system RAM allowing various models and types of CPUs to be supported. Supported CPUs are interchangeable in the system. In another aspect a default interface attached to the compressed I/O bus of the invention, and translates bus states between the optimized compressed bus and one of an ISA bus or an EISA bus.

Claims

1. A computer bus system connecting a CPU to connected peripheral devices, comprising:

a plurality of signal lines excluding any interrupt request (IRQ) lines but including address lines between said CPU and said connected peripheral devices, said connected peripheral devices assigning predetermined interrupt signals to predetermined addresses on said address lines and sending said predetermined interrupt signals to said CPU as said predetermined addresses on said address lines; and

an interrupt controller connected to said address lines, said interrupt controller being adapted to decode said predetermined addresses from said connected peripheral devices on said address lines as said predetermined interrupt signals from said connected peripheral devices to said CPU.

2. A computer bus system as in claim 1 additionally comprising a bus interface connected to said plurality of signal lines, the bus interface being adapted for translating bus states between said computer bus system and an industry standard computer bus system.

3. A computer bus system as in claim 2 wherein said industry standard computer bus system is one of an ISA bus, an EISA bus, or a Turbochannel bus.

4. A computer bus system as in claim 2 wherein said bus interface is a default device configured to respond I/O signals directed on said computer bus system to industry standard I/O devices connected to said industry standard computer bus system.

5. A computer bus system as in claim 1 wherein said plurality of signal lines comprise no more than 42 signal lines, and of the no more than 42 signal lines, a total of 32 lines are devoted to addresses and data, and wherein bus control circuitry multiplexes addresses and data on the 32 lines devoted to addresses and data.

6. A computer bus system as in claim 5 wherein said plurality of signal lines comprises a set of signal lines that are not address and data lines and wherein said set comprises 2 dedicated byte-enable lines, a dedicated CLK (clock) signal line, a dedicated address strobe line for starting a cycle and indicating a burst length, a dedicated device decode line for indicating that a device is claiming a cycle, a dedicated Ready line for indicating one of valid read data or a write word has been accepted, a dedicated read/write line driven simultaneously with the address signals, a dedicated bus request line for indicating a request by a peripheral device for bus ownership and specific to each peripheral device, a dedicated bus acknowledge signal line for bus acknowledge, also specific to each device, and a reset signal line to signal system reset.

7. A computer bus system as in claim 1 wherein said predetermined interrupt signals are mapped to particular high memory addresses addressable by said address lines.

8. A computer bus system as in claim 1 wherein input/output signals from/to said connected peripheral devices are sent to/from said CPU via an I/O address block at a certain address addressable by said address lines.

9. A computer bus system as in claim 1 wherein said interrupt controller includes registers which mimic a direct memory access (DMA) controller for processing DMA requests from said connected peripheral devices.

10. A computer system comprising:

a CPU;

a bus system excluding any interrupt request (IRQ) line but including address lines connecting said CPU to connected peripheral devices, said connected peripheral devices assigning predetermined interrupt signals to predetermined addresses on said address lines and sending said predetermined interrupt signals to said CPU as said predetermined address signals on said address lines; and

an interrupt controller connected to said CPU and to said address lines, said interrupt controller being adapted to decode said predetermined addresses from said connected peripheral devices on said address lines as said predetermined interrupt signals from said connected peripheral devices to said CPU.

11. A computer system as in claim 10 further comprising a programmable CPU interface, the programmable CPU interface having access to data tables and control routines stored in a memory connected to said programmable CPU interface, wherein data and control routines specific to a CPU type are selectable by said programmable CPU interface to operate individual ones of different types of CPUs.

12. A computer system as in claim 11 further comprising a cache memory connected to a local bus between said CPU and said programmable CPU interface for caching data between said CPU and said programmable CPU interface.

13. A computer system as in claim 10 further comprising a bus interface connected to said bus system for translating bus states between said bus system and an industry standard computer bus system.

14. A computer system as in claim 11 wherein said industry standard computer bus system is one of an ISA bus, an EISA bus, or a Turbochannel bus.

15. A computer system as in claim 13 wherein said bus interface is a default device configured to respond to I/O signals directed on said bus system to industry standard I/O devices connected to said industry standard computer bus system.

16. A computer system as in claim 10 wherein said bus system comprises no more than 42 signal lines, and of the no more than 42 lines, a total of 32 lines are dedicated to addresses and data, with addresses and data multiplexed on the 32 address and data lines.

17. A computer system as in claim 16 wherein said signal lines comprise a set of signal lines that are not address and data lines, said set comprising two dedicated byte-enable lines, a dedicated clock signal line, a dedicated address strobe line for starting a cycle and indicating a burst length, a dedicated device decode line for indicating that a device is claiming a cycle, a dedicated Ready line for indicating one of valid read data or a write word has been accepted, a dedicated read/write line driven simultaneously with the address signals, a dedicated bus request line for indicating a request by a peripheral device for bus ownership and specific to each peripheral device, a dedicated bus acknowledge signal line, also specific to each device, and a reset signal line to signal system reset.

18. A computer system as in claim 10 wherein said predetermined interrupt signals are mapped to particular high memory addresses addressable by said address lines.

19. A computer system as in claim 10 wherein input/output signals from/to said connected peripheral devices are sent to/from said CPU via an I/O address block at a certain address addressable by said address lines.

20. A computer system as in claim 10 wherein said interrupt controller includes registers which mimic a direct memory access (DMA) controller for processing DMA requests from said connected peripheral devices.

21. A method for issuing an interrupt request signal from a peripheral device connected to a computer bus having address and data lines and a bus request line, but no interrupt request lines, comprising the steps of:

(a) claiming use of the computer bus for the peripheral device by issuing a bus request from the peripheral device on the bus request line;

(b) assigning said interrupt request signal to a predetermined address on said address lines;

(c) the peripheral device issuing said predetermined address on the computer bus as said interrupt request signal for interrupting a system CPU;

(d) decoding the issued predetermined address at an interrupt controller connected to the computer bus and to said system CPU; and

(e) vectoring the CPU to execute a unique interrupt routine associated with the predetermined address issued by the peripheral device.

22. The method of claim 21 wherein the interrupt controller is adapted to vector the CPU to sixteen unique interrupt routines associated with sixteen unique addresses.

23. The method of claim 21 wherein said assigning step includes the step of mapping said predetermined interrupt signals to particular high memory addresses addressable by said address lines.

24. A method for reducing pinouts for a computer bus having an interrupt controller coupled to a CPU, comprising the steps of:

(a) removing all interrupt request lines;

(b) assigning predetermined addresses on an address line to unique interrupt routines;

(c) adapting the interrupt controller to vector the CPU to the unique interrupt routines pointed to by said predetermined addresses upon receipt of said predetermined addresses on said address line; and

(d) adapting peripheral devices connectable to the computer bus to issue at least one of said predetermined addresses in lieu of pulling an interrupt request line to begin an interrupt process.