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Structure and method for mapping interrupt requests in a high-speed CPU interconnect bus system

  • US 5,805,901 A
  • Filed: 11/12/1996
  • Issued: 09/08/1998
  • Est. Priority Date: 07/02/1993
  • Status: Expired due to Fees
First Claim
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1. A computer bus system connecting a CPU to connected peripheral devices, comprising:

  • a plurality of signal lines excluding any interrupt request (IRQ) lines but including address lines between said CPU and said connected peripheral devices, said connected peripheral devices assigning predetermined interrupt signals to predetermined addresses on said address lines and sending said predetermined interrupt signals to said CPU as said predetermined addresses on said address lines; and

    an interrupt controller connected to said address lines, said interrupt controller being adapted to decode said predetermined addresses from said connected peripheral devices on said address lines as said predetermined interrupt signals from said connected peripheral devices to said CPU.

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