Microprocessors or microcontroller utilizing FLL clock having a reduced power state
First Claim
1. A microprocessor or micro-controller formed as a single integrated circuit comprising:
- a plurality of similarly addressed modules at least one of said modules being an analog module or an analog interface module;
a clock circuit including a Frequency Locked Loop (FLL) circuit for clocking said microprocessor or micro-controller, said FLL circuit having two states, one of said states having a frequency lock loop active and the other of said states having said frequency lock loop inactive; and
a register under control of said microprocessor or micro-controller for controlling the state of said frequency lock loop.
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Accused Products
Abstract
A microprocessor or micro-controller of a module design and adapted for low power is described. Each of the modules is addressed and controlled by the CPU in the same way. All assembler instructions and all address modes can be applied to each module. Also, all 16 registers of the CPU are identical in character and can be used with each of the seven address modes. One such device is available in a 4K Byte or 8K Byte ROM, EPROM or RAM version (for prototyping). The high precision 12-bit A/D converter (which can be expanded to 14 bits without additional components) is combined with an LDC drive to output measurement results; the FET driver to switch on loads; the 8-bit Timer/Counter; several I/O ports which accept interrupts; and a watchdog which guarantees safe operation during unexpected events. Up to 16 nested interrupt levels (7 used in the first product) are active during all Processor/Power modes to capture various external events or timer results. A powerful set of only 51 assembler instructions and 76 address modes allow convenient and fast programming. The CPU can be programmed with minimal effort and a small number of code lines and is extremely economical with ROM space (the number of code lines for a task is a measurement of the programming time).
60 Citations
11 Claims
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1. A microprocessor or micro-controller formed as a single integrated circuit comprising:
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a plurality of similarly addressed modules at least one of said modules being an analog module or an analog interface module; a clock circuit including a Frequency Locked Loop (FLL) circuit for clocking said microprocessor or micro-controller, said FLL circuit having two states, one of said states having a frequency lock loop active and the other of said states having said frequency lock loop inactive; and a register under control of said microprocessor or micro-controller for controlling the state of said frequency lock loop. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. In a microprocessor or micro-controller having operations controlled by a clock signal, a power saving circuit comprising:
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a Frequency Locked Loop (FLL) circuit generating said clock signal, said FLL circuit having two states, one of said states having a frequency lock loop ON and the other of said states having said frequency lock loop OFF; and a register for storing at least one control bit for controlling said state of said frequency lock loop.
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Specification
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- Resources
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Current AssigneeTexas Instruments, Inc.
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Original AssigneeTexas Instruments, Inc.
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InventorsDiewald, Horst
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Primary Examiner(s)AUVE, GLENN ALLEN
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Application NumberUS08/510,808Time in Patent Office1,132 DaysField of Search395/750, 395/560, 395/559, 395/556, 395/750.04, 395/750.05, 364/482, 364/493US Class Current713/322CPC Class CodesG06F 1/3203 Power management, i.e. even...G06F 15/7814 Specially adapted for real ...G06F 9/4812 by interrupt, e.g. maskedY02D 10/00 Energy efficient computing,...
