Method for forming semiconductor device with bottom gate connected to source or drain

• US 5,807,772 A
• Filed: 06/05/1995
• Issued: 09/15/1998
• Est. Priority Date: 06/09/1992
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): Radomsky, Leon
• Application Number:
  US08/463,060
• Time in Patent Office: 1,198 Days
• Field of Search: 437/21, 437/40 TFI, 437/40 TFT, 437/41 TFT, 437/195, 437/228, 437/915, 437/41 TFI, 156/633.1, 156/634.1, 156/650.1-655.1, 156/657.1, 430/313, 430/314, 430/316, 430/317, 438/157, 438/161, 438/638, 438/640, 438/740
• US Class Current: 438/157
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

In a field effect type device having a thin film-like active layer, there is provided a thin film-like semiconductor device including a top side gate electrode on the active layer and a bottom side gate electrode connected to a static potential, the bottom side gate electrode being provided between the active layer and a substrate. The bottom side gate electrode may be electrically connected to only one of a source and a drain of the field effect type device. Also, the production methods therefor are disclosed.

Claims

1. A method of forming a semiconductor device comprising:

forming a conductive gate electrode on an insulating surface;

forming a first insulating film on said gate electrode;

forming a semiconductor film comprising source, drain and channel regions on said first insulating film;

forming a second insulating film on said semiconductor film;

forming a mask for etching on said second insulating film;

isotropically etching said second insulating film through an opening in said mask to form a contact hole in said second insulating film;

anisotropically etching said semiconductor film with said mask to form an opening in said semiconductor film;

etching said first insulating film with said mask to form an opening in said first insulating film; and

selectively forming a conductive electrode to electrically connect the gate electrode with the semiconductor film.

2. The method of claim 1 wherein said anisotropically etching step is carried out by reactive ion etching.

3. The method of claim 1 wherein said contact hole is wider than said opening of said mask by virtue of isotropy of said isotropically etching step.

4. The method of claim 1 wherein said contact hole formed in said second insulating film has a larger diameter than the opening opened in said semiconductor film so that said conductive electrode electrically contacts with an upper surface of said semiconductor film in said contact hole.