High frequency analog transistors method of fabrication and circuit implementation

• US 5,807,780 A
• Filed: 06/05/1995
• Issued: 09/15/1998
• Est. Priority Date: 09/27/1991
• Status: Expired due to Term

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Davis, Christopher K., Beasom, James D., Jung, Taewon, Bajor, George, Rivoli, Anthony L., Crandell, Thomas L.
• Primary Examiner(s): Dutton, Brian
• Application Number:
  US08/462,851
• Time in Patent Office: 1,198 Days
• Field of Search: 437/31, 437/59, 437/62, 437/21, 437/33, 437/40 R, 437/40 RG, 437/41 R, 437/41 RBP, 437/41 RG, 437/162, 257/588, 438/322, 438/311, 438/355
• US Class Current: 438/311
• CPC Class Codes: H01L 21/8228 Complementary devices, e.g. complementary transistors
• CPC Class Codes: H01L 21/82285 Complementary vertical transistors
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/082 including bipolar components only
• CPC Class Codes: H01L 27/0826 Combination of vertical complementary transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/7325 having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 29/8605 Resistors with PN junctions

Abstract

A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.

Claims

1. A method for making a pair of complementary bipolar transistors comprising the steps of:

forming a heavily doped N-type buried region in an electrically isolated semiconductor layer with N-type impurities;

forming a heavily doped P-type buried region in a second electrically isolated semiconductor layer with P-type impurities having a diffusion coefficient similar to the diffusion coefficient of the N-type impurities;

such that when thermally processed, the P-type and N-type impurities diffuse similar distances within respective semiconductor layers.

2. The method of claim 1 wherein the ratio of the diffusion coefficient of one of the P-type and N-type impurities to the differential coefficient of the other one of the impurities is in the range from 0.5 to 2.0.

3. The method of claim 1 wherein the P-type impurities are boron and the N-type impurities are phosphorous.

4. The method of claim 1 including the step of establishing a net dopant concentration in each transistor base region with an impurity of conductivity type different than that of the transistor'"'"'s heavily doped buried region, wherein the ratio of diffusion coefficients between the base impurities is in the range of 0.5 to 2.0.

5. The method of claim 4 wherein the step of establishing each transistor base region is performed to result in the separation distance between the base and buried region in each transistor being in the range from 0.7 to 1.5 microns.

6. The method of claim 4 including the steps of forming a lightly doped collector region adjoining the buried region of each transistor;

and

wherein for each transistor the base region includes a peak net dopant concentration at least fifty times the peak net dopant concentration in the lightly doped collector region.

7. The method of claim 1 wherein the semiconductor layers predominantly comprise monocrystalline silicon and the peak net dopant concentration in one of the buried region is predominantly established with a first concentration of impurity atoms having a smaller radius than atomic silicon, the method including the additional step of:

introducing impurity atoms having a larger radius than atomic silicon into said one buried region at a concentration less than the first concentration in order to reduce lattice defects.

8. A method of forming an integrated circuit structure comprising the steps of:

forming a layer of conductor material over a surface of a layer of semiconductor material;

forming an opening in the layer of conductive material which defines a wall extending through the layer of conductive material from an upper surface thereof to the semiconductor surface;

forming an oxide filament against the semiconductor surface and against the wall;

forming a nitride spacer against the wall with the oxide filament interposed between the spacer and the semiconductor surface.

9. The method of claim 8 wherein the spacer is isolated from the semiconductor surface by the filament.

10. The method of claim 8 wherein the steps of forming the filament and spacer include:

sequentially forming a layer of oxide and nitride in the opening;

etching through the nitride layer to define a second opening extending through the nitride spacer to the oxide layer;

extending the second opening through the oxide layer to expose the semiconductor surface with an etchant more selective to oxide than nitride.

11. The method of claim 10 wherein the second opening is etched through the oxide layer with a buffered HF solution leaving the filament against the wall.

12. A process of fabricating an integrated circuit in a plurality of isolated islands on a wafer comprising:

forming first insulative regions having openings which expose at least the base area of a first island of a first conductivity type in which a bipolar transistor is to be formed;

forming a first layer of polycrystalline semiconductor on said wafer;

selectively doping portions of said first polycrystalline layer contracting said base area of said first island with impurities of a second conductivity type to form a base conductor;

forming a second insulative layer over said wafer;

removing a portion of said base conductor and superimposed second insulative layer to expose an intrinsic base area of said first island;

forming a third insulative layer over said exposed intrinsic base area;

diffusing said impurities from said base conductor into said first island to form an extrinsic base region;

selectively introducing second conductivity type impurities into said intrinsic base area of said first island to form and intrinsic base region;

forming lateral spacers on the lateral walls of said base conductor and on said third insulative layer adjacent said intrinsic base area, with exposed portions of said third insulative layer therebetween, and separated from said intrinsic base region by said third insulative layer,

selectively removing said exposed portions of said third insulative layer to thereby expose a portion of said intrinsic base area between the later spacers; and

introducing impurities of said first conductivity type into said intrinsic base regions between the lateral spacers to form an emitter region, with the spacing between the emitter nad the extrainsic base being essentially determined by the thickness of the lateral spacers.

13. The process of claim 12, wherein the step of introducing impurities to form said emitter region includes:

forming a second layer of polycrystalline semiconductor on said wafer;

selectively doping portions of said second polycrystalline layer contacting said intrinsic base area of said first island with said first conductivity type impurities to form an emitter conductor; and

diffusing impurities from said emitter conductor into said first island to form said emitter region.

14. A method for fabricating a bipolar transistor having extrinsic and intrinsic base regions along a semiconductor surface with an emitter region formed within the intrinsic base region, comprising the steps of:

etching a first opening to expose the semiconductor surface for formation of an intrinsic base region;

forming an intrinsic base region in the surface;

forming a first insulator layer on the intrinsic base region exposed in the first opening;

forming a layer of a spacer material along the side walls of the first opening and on the exposed first insulator layer;

etching a second opening through the spacer material and first insulator layer within the first opening for emitter formation so that the spacer material formed on the side walls of the first opening to thereby define the second opening is separated from the surface by the first insulator layer; and

forming the emitter region in the semiconductor surface through the second opening.

15. The method of claim 14 wherein the etch rate of the etchant used in the step of etching the second opening through the spacer material is greater for the spacer material than for the first insulator layer.

16. The method of claim 15 wherein at least the spacer material is anisotropically etched.

17. The method of claim 16 wherein the anisotropic etch does not etch all the way through the first insulator layer.

18. The method of claim 17 including the step of etching away any residual material of the exposed first insulator layer without damaging the semiconductor surface and without removing material of the semiconductor surface.

19. The method of claim 18 wherein the etch used to remove any residual insulator layer is a wet etch.

20. The method of claim 19 where the first insulator layer is an oxide.

21. The method of claim 20 where the spacer material is a nitride.

22. The method of claim 14 where the spacer material is a nitride.

23. The method of claim 14 where the spacer material is polysilicon.

24. The method of claim 14 where the insulator layer is an oxide.

25. The method of claim 14 wherein the intrinsic base region is formed by a dopant implant aligned with the first opening.

26. The method of claim 14 wherein the emitter region is formed with the spacer material formed on the side walls of the first opening.

27. In a method for fabricating the base along a semiconductor surface wherein the semiconductor surface is exposed in a first opening and extrinsic base region is formed in the semiconductor surface, the improvement comprising the steps of:

(a) forming an insulator layer on the extrinsic base region exposed in the first opening;

(b) forming a layer of a spacer material along the side walls of the first opening and on the exposed insulator layer;

(c) anisotropically etching the spacer material to remove less than all of the exposed insulator layer; and

(d) etching away any residual material of the exposed insulator layer without damaging the semiconductor surface and without removing material of the semiconductor surface.

28. The method of claim 27 wherein the spacer material is either a nitride or a polysilicon;

and

wherein the insulator layer is an oxide.

29. The method of claim 27 wherein the step of anisotropically etching the spacer material to remove less than all of the insulator layer leaves a layer of spacer material on the side walls of the first opening.

30. In a method for fabricating a bipolar transistor having extrinsic and intrinsic base regions along a semiconductor surface with an emitter region formed between spacers within the intrinsic base region, the improvement comprising the step of separating the spacers from the semiconductor surface by a thin oxide film.

31. The method of claim 30 wherein the spacers are a nitride.

32. A method for fabricating a bipolar transistor having extrinsic and intrinsic base regions along a semiconductor surface with an emitter region formed within the intrinsic base region, comprising the steps of:

exposing the semiconductor surface for formation of the intrinsic base region;

forming the extrinsic base region in the semiconductor surface;

forming a thin oxide layer on the base region exposed in the first opening;

forming a dielectric film on the thin oxide layer within the first opening;

dry etching the first opening with selectivity to the thin oxide to form a dielectric spacer on the side walls and expose the thin oxide;

etching with HF to remove the exposed thin oxide; and

depositing polysilicon in the second opening to form the emitter in the semiconductor surface.