Method for reducing surface leakage current on semiconductor intergrated circuits during polyimide passivation

• US 5,807,787 A
• Filed: 12/02/1996
• Issued: 09/15/1998
• Est. Priority Date: 12/02/1996
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lan, Ho-Ku, Chao, Ying-Chen, Fu, Wen-Jui
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): Berry, Renee R.
• Application Number:
  US08/755,862
• Time in Patent Office: 652 Days
• Field of Search: 437/231, 437/183, 437/43, 438/630, 438/974, 438/603, 438/623, 438/688
• US Class Current: 438/623
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: Y10S 438/974 Substrate surface preparation

Abstract

A method is achieved for reducing the surface leakage current between adjacent bonding pads on integrated circuit substrates after forming a patterned polyimide passivation layer. When the polyimide layer is patterned to open contacts areas over the bonding pads, plasma ashing in oxygen is used to remove residual polyimide that otherwise causes high contact resistance, and poor chip yield. This plasma ashing also modifies the insulating layer between bonding pads resulting in an unwanted increase in surface leakage currents between bonding pads. The passivation process is improved by using a thermal treatment step in either a nitrogen or air ambient after the plasma ashing to essentially eliminate the increased surface leakage current and improve chip yield.

Claims

1. A method of forming a polyimide passivation layer on semiconductor integrated circuits with reduced surface leakage currents between bonding pads, comprising the steps of;

providing a semiconducting substrate having semiconductor devices formed in and on said substrate, said semiconductor devices electrically connected by a multilayer of patterned electrical conducting layers and alternate insulating layers having interconnecting contact openings between said patterned conducting layers, and thereby providing said semiconductor integrated circuits;

depositing a top insulating layer;

etching contact openings in said top insulating layer to portions of said semiconductor integrated circuits;

forming an array of electrically conductive bonding pads on said top insulating layer and over said contact openings;

depositing a first passivation layer on said bonding pads and elsewhere on said substrate;

etching openings in said first passivation layer over and to the surface of said bonding pads;

depositing by spin coating a second passivation layer, composed of polyimide, on said first passivation layer and in said etched openings over said bonding pads;

patterning said polyimide second passivation layer removing portions over said array of bonding pads and over said first passivation layer between said bonding pads;

plasma ashing in oxygen said substrate surface, and thereby removing polyimide residue on said bonding pads, said plasma ashing also causing an increase in the surface leakage current on said first passivation layer between said bonding pads;

thermally treating said substrate, and thereby eliminating said increase in surface leakage current, and provide a polyimide passivation layer on said semiconductor integrated circuits having reduced surface leakage currents between said bonding pads.

2. The method of claim 1, wherein said bonding pads are composed of an aluminium/copper (Al/Cu) alloy.

3. The method of claim 1, wherein the thickness of said bonding pads is between about 4000 and 8000 Angstroms.

4. The method of claim 1, wherein said first passivation layer is silicon oxide/silicon nitride (SiO₂ /Si₃ N₄) deposited by chemical vapor deposition (CVD).

5. The method of claim 1, wherein the thickness of said first passivation layer is between about 4000 and 12000 Angstroms.

6. The method of claim 1, wherein said second passivation layer is a photosensitive polyimide.

7. The method of claim 1, wherein the thickness of said second passivation layer is between about 3.0 and 12.0 micrometers (μ

m).

8. The method of claim 6, wherein said patterning of said photosensitive polyimide is achieved by cross-linking with ultra violet (UV) radiation through a mask while masking from UV exposure polyimide regions over said bonding pads, and dissolving away in a solvent the non-crosslinked polyimide over said bonding pad areas.

9. The method of claim 1, wherein, said thermal treatment is in a nitrogen (N₂) gas ambient at a temperature of between about 250°

and 400°

C. for a time equal to or greater than 1.0 hour.

10. The method of claim 1, wherein, said thermal treatment is in air ambient at a temperature of between about 220°

to 280°

C. for a time equal to or greater than 3.0 minutes.

11. The method of claim 1, wherein said thermal treatment after said oxygen plasma ashing reduces said surface leakage current between said bonding pads by an order of magnitude.

12. The method of claim 1, wherein said thermal treatment after said oxygen plasma ashing reduces the surface leakage current from between about 1.0 to 2.0 nanoampere to between about 0.1 to 0.2 nanoampere.

13. A method of forming a polyimide passivation layer on semiconductor integrated circuits with reduced surface leakage currents between bonding pads, comprising the steps of;

providing a semiconducting substrate having semiconductor devices formed in and on said substrate, said semiconductor devices electrically connected by a multilayer of patterned electrical conducting layers and alternate insulating layers having interconnecting contact openings between said patterned conducting layers, and thereby providing said semiconductor integrated circuits;

depositing a top insulating layer;

etching contact openings in said top insulating layer to portions of said semiconductor integrated circuits;

forming an array of electrically conductive bonding pad on said top insulating layer and over said contact openings composed of aluminium;

depositing a first passivation layer on said bonding pads and elsewhere on said substrate composed of silicon oxide;

etching openings in said first passivation layer over and to the surface of said bonding pads;

depositing by spin coating a second passivation layer, composed of a photosensitive polyimide, on said first passivation layer and in said etched openings over said bonding pads;

patterning said polyimide second passivation layer removing portions over said array of bonding pads and over said first passivation layer between said bonding pads;

plasma ashing in oxygen said substrate surface, and thereby removing polyimide residue on said bonding pads, said plasma ashing also causing an increase in the surface leakage current on said first passivation layer between said bonding pads;

thermally treating said substrate in a nitrogen (N₂) ambient, and thereby eliminating said increase in surface leakage current, and provide a polyimide passivation layer on said semiconductor integrated circuits having reduced surface leakage currents between said bonding pads.

14. The method of claim 13, wherein said bonding pads are formed by depositing an aluminium (Al) layer and patterning using a photoresist etch mask and etching.

15. The method of claim 13, wherein said bonding pads are formed by physical evaporation of aluminium through a metal mask aligned over the substrate.

16. The method of claim 13, wherein the thickness of said bonding pads is between about 4000 and 8000 Angstroms.

17. The method of claim 13, wherein said first passivation layer composed of silicon oxide/silicon nitride (SiO₂ /Si₃ N₄) is deposited by chemical vapor deposition (CVD).

18. The method of claim 13, wherein the thickness of said first passivation layer is between about 7000 and 12000 Angstroms.

19. The method of claim 13, wherein the thickness of said second passivation layer is between about 3.0 and 12.0 micrometers (μ

m).

20. The method of claim 13, wherein said patterning of said photosensitive polyimide is achieved by cross-linking with ultra violet (UV) radiation through a mask while masking from UV exposure polyimide regions over said bonding pads, and dissolving away in a solvent the non-crosslinked polyimide over said bonding pad areas.

21. The method of claim 13, wherein, said thermal treatment in said nitrogen (N₂) gas ambient is at a temperature of between about 250°

and 400°

C. for a time equal to or greater than 1.0 hour.

22. The method of claim 13 wherein said thermal treatment after said oxygen plasma ashing reduces said surface leakage current between said bonding pads by an order of magnitude.

23. The method of claim 13 wherein said thermal treatment after said oxygen plasma ashing reduces the surface leakage current from between about 1.0 to 2.0 nanoampere to between about 0.1 to 0.2 nanoampere.