Integrated circuits, and methods of fabricating same, which take into account capacitive loading by the integrated circuit potting material
First Claim
1. An integrated circuit comprising:
- a plurality of microelectronic devices in a microelectronic substrate;
a plurality of conductive interconnect layers on said microelectronic substrate, said plurality of microelectronic layers including an outer conductive interconnect layer having a plurality of conductive regions;
a passivating layer on said outer conductive interconnect layer, which fills the spaces between the plurality of conductive regions in said outer conductive layer; and
a potting material on said passivating layer, said passivating layer blocking said potting material from extending between said plurality of conductive regions in said outer conductive layer so that the capacitive load of the potting material on the outer conductive interconnect layer is eliminated.
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Accused Products
Abstract
High speed integrated circuits are designed and fabricated by taking into account the capacitive loading on the integrated circuit by the integrated circuit potting material. Line drivers may be sized to drive conductive lines as capacitively loaded by the potting material. Repeaters may be provided along long lines, to drive the lines as capacitively loaded by the potting material. Intelligent drivers may sense the load due to the potting material and drive the lines as capacitively loaded by the potting material. The thickness of the passivating layer on the outer conductive lines may also be increased so as to prevent the potting material from extending between the conductive lines. High speed potted integrated circuits may thereby be provided.
6 Citations
2 Claims
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1. An integrated circuit comprising:
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a plurality of microelectronic devices in a microelectronic substrate; a plurality of conductive interconnect layers on said microelectronic substrate, said plurality of microelectronic layers including an outer conductive interconnect layer having a plurality of conductive regions; a passivating layer on said outer conductive interconnect layer, which fills the spaces between the plurality of conductive regions in said outer conductive layer; and a potting material on said passivating layer, said passivating layer blocking said potting material from extending between said plurality of conductive regions in said outer conductive layer so that the capacitive load of the potting material on the outer conductive interconnect layer is eliminated. - View Dependent Claims (2)
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Specification
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- Resources
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Current AssigneeMOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
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Original AssigneeSamsung Electronics Co. Ltd.
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InventorsSong, Minkyu
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Primary Examiner(s)Jackson, Jerome
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Assistant Examiner(s)GUAY, JOHN FRANCIS
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Application NumberUS08/694,541Time in Patent Office767 DaysField of Search257/923, 257/787, 257/794, 257/790, 257/635, 257/644, 257/650, 257/752US Class Current257/794CPC Class CodesH01L 23/5222 Capacitive arrangements or ...H01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...Y10S 257/923 with means to optimize elec...
